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Datasheet File OCR Text:

STM8AF61xx, STM8H61xx STM8AF51xx, STM8AH51xx
Automotive 8-bit MCU, with up to 128 Kbytes Flash, EEPROM, 10-bit ADC, timers, LIN, CAN, USART, SPI, I2C, 3 V to 5.5 V
Features
Core
Max fCPU: 24 MHz Advanced STM8A core with Harvard architecture and 3-stage pipeline Average 1.6 cycles/instruction resulting in 10 MIPS at 16 MHz fCPU for industry standard benchmark
LQFP48 7x7
LQFP80 14x14
LQFP64 10x10 LQFP32 7x7
Memories
Communication interfaces

Program memory: 48 to 128 Kbytes Flash; data retention 20 years at 55 C after 1 kcycle Data memory: 1.5 to 2 Kbytes true data EEPROM; endurance 300 kcycles RAM: 3 to 6 Kbytes
Clock management
Low power crystal resonator oscillator with external clock input Internal, user-trimmable 16 MHz RC and low power 128 kHz RC oscillators Clock security system with clock monitor
High speed 1 Mbit/s active CAN 2.0B interface USART with clock output for synchronous operation - LIN master mode LINUART LIN 2.1 compliant, master/slave modes with automatic resynchronization SPI interface up to 10 Mbit/s or (fCPU/2) 2 I C interface up to 400 Kbit/s
Analog to digital converter (ADC)
10-bit, 3 LSB ADC with up to 16 multiplexed channels Up to 70 user pins including 10 high sink I/Os Highly robust I/O design, immune against current injection Device summary(1)
I/Os

Reset and supply management
Multiple low power modes (wait, slow, auto wake-up, halt) with user definable clock gating Low consumption power-on and power-down reset
Table 1.
Interrupt management
STM8AF61xx/STM8AH61xx (without CAN) STM8AF/H61AA, STM8AF/H619A, STM8AF/H61A9, STM8AF/H6199, STM8AF/H6189, STM8AF/H6179, STM8AF/H6169, STM8AF/H61A8, STM8AF/H6198, STM8AF/H6188, STM8AF/H6178, STM8AF/H6186, STM8AF/H6176 STM8AF51xx/STM8AH51xx (with CAN) STM8AF/H51AA, STM8AF/H519A, STM8AF/H51A9, STM8AF/H5199, STM8AF/H5189, STM8AF/H5179, STM8AF/H5169, STM8AF/H51A8, STM8AF/H5198, STM8AF/H5188, STM8AF/H5178
1. This datasheet applies to product versions with and without data EEPROM. The order code identifier is `F' or `H' respectively, only one of which appears in an order code.
Nested interrupt controller with 32 interrupt vectors Up to 37 external interrupts on 5 vectors
Timers

Up to 2 auto-reload 16-bit PWM timers with up to 3 CAPCOM channels each (IC, OC or PWM) Multipurpose timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization 8-bit AR system timer with 8-bit prescaler Auto wake-up timer 2 watchdog timers: Window and standard
August 2008
Rev 2
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Contents
STM8AF61xx, STM8AF51xx
Contents
1 2 3 4 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Product line-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Central processing unit STM8A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1 5.1.2 5.1.3 Architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2
Single wire interface module (SWIM) and debug module . . . . . . . . . . . . 13
5.2.1 5.2.2 SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 5.4
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Non-volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4.1 5.4.2 5.4.3 5.4.4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write protection (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read-out protection (ROP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5 5.6
Low-power operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Clock and clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Internal 16 MHz RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Internal 128 kHz RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Internal high-speed crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 External clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.7
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7.1 5.7.2 5.7.3 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Auto wake-up counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Multipurpose and PWM timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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STM8AF61xx, STM8AF51xx 5.7.4
Contents Timer 4: System timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.8 5.9
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.9.1 5.9.2 5.9.3 5.9.4 5.9.5 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 LINUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.10
Input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1 6.2 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.1 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7 8 9 10 11
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
11.1.1 11.1.2 11.1.3 11.1.4 11.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.2 11.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 67 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 69 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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Contents 11.3.6 11.3.7 11.3.8 11.3.9
STM8AF61xx, STM8AF51xx Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TIM 1, 2, 3, and 4 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 78 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 11.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.4
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.4.1 11.4.2 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 89
12
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
13 14
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
14.1 14.2 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 96 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.2.1 14.2.2 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
14.3
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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STM8AF61xx, STM8AF51xx
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM8AF/H51xx product line-up - with CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STM8AF/H61xx product line-up - without CAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STM8A timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Legend/abbreviation for Table 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 STM8A microcontroller family pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Stack and RAM partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STM8A interrupt table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STM8A I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STM8A general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Total current consumption in run, wait and slow mode at VDD = 5.0 V. . . . . . . . . . . . . . . . 59 Total current consumption and timing in halt, fast active halt and slow active halt modes at VDD = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Total current consumption in run, wait and slow mode at VDD = 3.3 V. . . . . . . . . . . . . . . . 61 Total current consumption and timing in halt, fast active halt and slow active halt modes at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Typical peripheral current consumption VDD = 5.0 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TIM 1, 2, 3 characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ADC accuracy with RAIN < 10 k RAIN, VDDA = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ADC accuracy with RAIN < 10 k , VDDA = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 64-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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List of tables Table 47.
STM8AF61xx, STM8AF51xx
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. STM8A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 STM8A products: Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 LQFP 32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Typ. IDD(RUN)HSE vs. VDD @fCPU = 16 MHz, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typ. IDD(RUN)HSE vs. fCPU @ VDD = 5.0 V, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typ. IDD(RUN)HSI vs. VDD @ fCPU = 16 MHz, periph = off . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typ. IDD(WFI)HSE vs. VDD @ fCPU = 16 MHz, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typ. IDD(WFI)HSE vs. fCPU @ VDD = 5.0 V, periph = on . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typ. IDD(WFI)HSI vs. VDD @ fCPU = 16 MHz, periph = off . . . . . . . . . . . . . . . . . . . . . . . . . . 66 HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Typical HSI frequency vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Typical LSI frequency vs VDD @ room temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical VIL and VIH vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typical pull-up resistance RPU vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . 73 Typical pull-up current Ipu vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typ. VOL @ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typ. VOL @ VDD = 5.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typ. VOL @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typ. VDD - VOH @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typ. VDD - VOH @ VDD = 5.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typ. VDD - VOH @ VDD = 5.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typical NRST VIL and VIH vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typical NRST pull-up resistance RPU vs VDD @ four temperatures. . . . . . . . . . . . . . . . . . 77 Typical NRST pull-up current Ipu vs VDD @ four temperatures . . . . . . . . . . . . . . . . . . . . . 77 Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 STM8A order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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1
Introduction
This datasheet refers to the STM8AF61xx, STM8AH61xx, STM8AF51xx, STM8AH51xx products with 48 to 128 Kbytes of program memory. The STM8AF51xx and STM8AH51xx are hereafter referred to as the STM8AF/H51xx and the STM8AF61xx and STM8AH61xx are hereafter referred to as the STM8AF/H61xx. `F' refers to product versions with data EEPROM and `H' refers to product versions without EEPROM. The identifiers `F' and `H' do not both appear in an order code. The datasheet contains the description of family features, pinout, electrical characteristics, mechanical data and ordering information.

For complete information on the STM8A microcontroller memory, registers and peripherals, please refer to STM8A microcontroller family reference manual (RM0009). For information on programming, erasing and protection of the internal Flash memory please refer to the STM8 Flash programming manual (PM0047). For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470). For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044).
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Description
2
Description
The STM8A automotive 8-bit microcontrollers offer from 48 to 128 Kbytes of program memory and integrated true data EEPROM. The STM8AF/H51xx series feature a CAN interface. All devices of the STM8A product line provide the following benefits:
Reduced system cost - - Integrated true data EEPROM for up to 300 k write/erase cycles High system integration level with internal clock oscillators, watchdog and brownout reset Peak performance 20 MIPS at 24 MHz and average performance 10 MIPS at 16 MHz CPU clock frequency Robust I/O, independent watchdogs with separate clock source Clock security system Applications scalability across a common family product architecture with compatible pinout, memory map and and modular peripherals. Full documentation and a wide choice of development tools Advanced core and peripherals made in a state-of-the art technology Native automotive product family operating both at 3.3 V and 5 V supply
Performance and robustness - - -
Short development cycles - -
Product longevity - -
All STM8A and ST7 microcontrollers are supported by the same tools including STVD/STVP development environment, the STice emulator and a low-cost, third party incircuit debugging tool (for more details, see Section 14: STM8 development tools on page 96).
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Product line-up
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3
Table 2.
.
Product line-up
STM8AF/H51xx product line-up - with CAN
Package LQFP80 (14x14) Prog. RAM Data EE 10-bit (bytes) (bytes) (bytes) A/D ch. 128 K 72/37 96 K 6K 2K 16 4K 1.5 K 48 K 32 K 128 K 6K 2K 10 64 K 48 K 4K 1.5 K 3K 40/35 LQFP48 (7x7)(1) 96 K 3K 2K 1K 1x8-bit: TIM4 CAN, 3x16-bit: TIM1, LIN(UART), TIM2, TIM3 SPI, USART, (9/9/9) IC 56/36 128 K 96 K LQFP64 (10x10) 64 K Timers (IC/OC/PWM) Serial interfaces I/0 wakeup pins
Order code STM8AF/H51AAT STM8AF/H519AT STM8AF/H51A9T STM8AF/H5199T STM8AF/H5189T STM8AF/H5179T STM8AF/H5169T STM8AF/H51A8T STM8AF/H5198T STM8AF/H5188T STM8AF/H5178T
1. QFN package planned
Table 3.
STM8AF/H61xx product line-up - without CAN
Package Prog. RAM Data EE 10-bit (bytes) (bytes) (bytes) A/D ch. 128 K 72/37 96 K 6K 2K 16 4K 1.5 K 48 K 32 K 128 K 6K 2K 10 64 K 48 K 64 K LQFP32 (7x7)(1) 48 K 4K 3K 4K 3K 1.5 K 7 1x8-bit: TIM4 3x16-bit: TIM1, TIM2, TIM3 (8/8/8) LIN(UART), SPI, IC 40/35 LQFP48 (7x7)(1) 96 K 3K 2K 1K 1x8-bit: TIM4 3x16-bit: TIM1, TIM2, TIM3 (9/9/9) LIN(UART), SPI, USART, IC 56/36 128 K 96 K LQFP64 (10x10) 64 K Timers (IC/OC/PWM) Serial interfaces I/0 wakeup pins
Order code STM8AF/H61AAT STM8AF/H619AT STM8AF/H61A9T STM8AF/H6199T STM8AF/H6189T STM8AF/H6179T STM8AF/H6169T STM8AF/H61A8T STM8AF/H6198T STM8AF/H6188T STM8AF/H6178T STM8AF/H6186T STM8AF/H6176T
LQFP80 (14x14)
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Block diagram
4
Block diagram
Figure 1. STM8A block diagram
Reset block Clock controller Reset Reset
XTAL 1-24 MHz
RC int. 16 MHz Detector POR PDR RC int. 128 kHz
Clock to peripherals and core
Window WDG STM8A CORE WDG Single wire debug interf.
Debug/SWIM
Up to 128 Kbyte program Flash Up to 2 Kbytes data EEPROM Up to 6 Kbytes RAM Boot ROM
Master/slave autosynchro
LINUART Address and data bus
400 Kbit/s
I2C
10 Mbit/s
SPI
LIN master SPI emul.
USART
16-bit multi-purpose timer (TIM1) 16-bit PWM timers (TIM2, TIM3) 8-bit AR timer (TIM4)
Up to 9 CAPCOM channels
1 Mbit/s
beCAN
16 channels
10-bit ADC
AWU timer
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Product overview
STM8AF61xx, STM8AF51xx
5
Product overview
The following section intends to give an overview of the basic features of the STM8A functional modules and peripherals. For more detailed information please refer to the STM8A microcontroller family reference manual (RM0009).
5.1
Central processing unit STM8A
The 8-bit STM8A core is designed for code efficiency and performance. It contains 21 internal registers (six directly addressable in each execution context), 20 addressing modes including indexed indirect and relative addressing and 80 instructions.
5.1.1
Architecture and registers

Harvard architecture 3-stage pipeline 32-bit wide program memory bus with single cycle fetching for most instructions X and Y 16-bit index registers, enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter with 16-Mbyte linear memory space 16-bit stack pointer with access to a 64 Kbyte stack 8-bit condition code register with seven condition flags for the result of the last instruction
5.1.2
Addressing

20 addressing modes Indexed indirect addressing mode for look-up tables located anywhere in the address space Stack pointer relative addressing mode for local variables and parameter passing
5.1.3
Instruction set

80 instructions with 2-byte average instruction size Standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division Bit manipulation Data transfer between stack and accumulator (push/pop) with direct stack access Data transfer using the X and Y registers or direct memory-to-memory transfers
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Product overview
5.2
Single wire interface module (SWIM) and debug module
The single wire interface module, SWIM, together with an integrated debug module, permits non-intrusive, real-time in-circuit debugging and fast memory programming.
5.2.1
SWIM
Single wire interface for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes and supports hot-plugging. The maximum data transmission speed is 145 bytes/ms.
5.2.2
Debug module
The non-intrusive debugging module features a performance close to a full-featured emulator. Besides memory and peripheral operation, CPU operation can also be monitored in real-time by means of shadow registers.

R/W of RAM and peripheral registers in real-time R/W for all resources when the application is stopped Breakpoints on all program-memory instructions (software breakpoints) except the vector table Two advanced breakpoints and 23 predefined configurations
5.3
Interrupt controller

Nested interrupts with three software priority levels 32 interrupt vectors with hardware priority Up to 37 external interrupts on five vectors Trap and reset interrupts
5.4
Non-volatile memory

Up to 128 Kbytes of program single voltage Flash memory Up to 2 Kbytes true (not emulated) data EEPROM Read while write: Writing in the data memory is possible while executing code in the program memory 128 user option bytes permit permanent device set up
5.4.1
Architecture

Array: Up to 128 Kbytes of Flash program memory organized in blocks of 128 bytes each Read granularity: 1 word = 4 bytes Write/erase granularity: 1 word (4 bytes) or 1 block (128 bytes) in parallel
Writing, erasing, word and block register management is handled automatically by the memory interface.
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5.4.2
Write protection (WP)
Write protection in application mode is intended to avoid unintentional overwriting of the memory in case of user software malfunction. Code update in user mode is still possible after execution of a specific MASS key sequence. The program memory is divided into two areas:

Main program memory: Up to 128 Kbytes minus user-specific boot code (UBC) UBC: Configurable up to 128 Kbytes
The UBC area also remains write-protected during in-application programming. It permits storage of the boot program or specific code libraries. The boot area is a part of the program memory that contains the reset and interrupt vectors, the reset routine and usually the IAP and communication routines. The UBC area has a second level of protection to prevent unintentional erasing or modification during IAP programming. This means that the MASS keys do not unlock the UBC area. The size of the UBC is programmable through the UBC option byte, in increments of 512 bytes, by programming the UBC option byte in ICP mode. Figure 2. STM8A products: Flash memory organization
UBC area Remains write protected during IAP
Programmable area from 1 Kbyte (first two pages) up to program memory end - maximum 128 Kbytes
Flash program memory Program memory area Write access possible for IAP
Data EEPROM memory
Data memory area (2 Kbytes)
Option bytes
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Product overview
5.4.3
Read-out protection (ROP)
STM8A devices provide a read-out protection of the code and data memory by programming the lock byte at address 4800h with the value AAh. Read-out protection prevents reading and writing the program and data memory via the debug module and SWIM interface. This protection is active in all device operation modes. Any attempt to remove the protection by overwriting the lock byte triggers a global erase of the program and data memory. The ROP circuit may provide a temporary access for debugging or failure analysis. This is a specific product option and must be specified while ordering STM8A products. Temporary read access is protected by a user defined, 8-byte keyword that is different from 00h or FFh. The keys are stored in the option byte area. Temporary read-out can be permanently disabled by means of the option byte TMU_DIS. For enabling temporary read access the eight access keys have to be written in the TMU registers. A wrong code does not change the protection status. More than eight unsuccessful access trials trigger an erase of the program and data memory. Entering the right key sequence enables a temporary read access to the code and data memory after a delay of several milliseconds. The procedure for temporary read access is as follows:

Activate SWIM mode under device reset - the CPU is stalled, code and data memory are not visible by the debug module. Enable the internal 128 KHz LSI oscillator Write the 8eight key bytes into the TMU registers Set the bit(0) of the TMU status register to 1. A dedicated state machine on an isolated bus, compares the TMU register content with the key stored in the TMU option bytes. During this periode read and write operations have no effect. A reset re-activates the initial protection status. The comparison can be monitored by means of the TU_CTL_ST register. In case of a successful key comparison, the SWIM interface enables read access to the code and data memory and program execution. A comparison error does not change the protection status but increments the counter MAXATT. If the counter content exceedes eight unsuccessful trials, a global erase of the data and code memory is triggered.
The read access is temporary. A device reset restores the initial protection.
5.4.4
Speed

Operation at up to 16 MHz CPU clock frequency without wait states. At a higher clock frequency, a single wait state has to be inserted. Programming time modes (same for word or block) - - Fast programming: Without erase Standard programming: Erase and program
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5.5
Low-power operating modes
The product features various low-power modes:

Slow mode: Prescaled CPU clock, selected peripherals at full clock speed Active halt mode: CPU and peripheral clocks are stopped Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. Wake-up is triggered by an external interrupt.
In all modes the CPU and peripherals remain permanently powered on, the system clock is applied only to selected modules. The RAM content is preserved and the brown-out reset circuit remains activated.
5.6
Clock and clock controller
The clock controller distributes the system clock coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.
5.6.1
Features
Clock sources: - - - Internal 16 MHz and 128 kHz RC oscillators Crystal oscillator External clock input
Reset: After reset the microcontroller restarts by default with an internal 2-MHz clock (16 MHz/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching. Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. Wake-up: Recovery from halt and AWU (auto wake-up) low power modes uses the internal RC oscillator (16 MHz/8) for quick start-up and then switches to the last selected clock source before halt mode is entered. Clock security system (CSS): The CSS permits monitoring of external clock sources and automatic switching to the internal RC (16 MHz/8) in case of a clock failure. Configurable main clock output (CCO): This outputs an external clock for use by the application.

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Product overview
5.6.2
Internal 16 MHz RC oscillator

Default clock after reset 2 MHz (16 MHz/8) Wake-up time: < 2 s
User trimming
The register CLK_HSITRIMR with two trimming bits plus one additional bit for the sign permits frequency tuning to a precision of 1% by the application program. The trimming step granularity is 1.5 %. The adjustment range covers all possible frequency variations versus supply voltage and temperature. This trimming does not change the initial production setting.
5.6.3
Internal 128 kHz RC oscillator
The frequency of this clock is 128 kHz and it is independent from the main clock. It drives the watchdog or the AWU wake-up timer. In systems which do not need independent clock sources for the watchdog counters, the 128 kHz signal can be used as the system clock. This configuration has to be enabled by setting an option byte (OPT3, LSI_EN).
5.6.4
Internal high-speed crystal oscillator
The internal high-speed crystal oscillator delivers the main clock in normal run mode. It operates with quartz crystals and ceramic resonators.

Frequency range: 1 to 24 MHz Crystal oscillation mode: Preferred fundamental I/Os: Standard I/O pins multiplexed with OSCIN, OSCOUT
Optionally, an external clock signal can be injected into the OSCIN input pin.
5.6.5
External clock input
The external clock signal is applied to the OSCIN input pin of the crystal oscillator. The frequency range is 0 to 24 MHz.
5.6.6
Clock security system (CSS)
The clock security system protects against a system stall in case of an external crystal clock failure. In case of a clock failure an interrupt is generated and the high speed internal clock (HSI) is automatically selected with a frequency of 2 MHz (16 MHz/8). This function can be enabled using the CSS register (CLK_CSSR). The CSS operates by detecting when the external clock signal (crystal or external clock) falls below 500 kHz. With active CSS this is the minimum operating frequency.
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Product overview
STM8AF61xx, STM8AF51xx
5.7
5.7.1
Timers
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to the applications. The WDG timer activity is controlled by the application program or option bytes. Once the watchdog is activated, it cannot be disabled by the user program without a reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application perfectly. The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 1. 2. Timeout Refresh out of window: The downcounter is refreshed before its value is lower then the one stored in the window register.
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure. If the hardware watchdog feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the key register is written by software before the counter reaches the end of count. The IWDG time base spans from 60 s to 1 s. It can be adjusted by setting the registers of the 7-bit prescaler and 8-bit down-counter.
5.7.2
Auto wake-up counter

Used for auto wake-up from active halt mode. Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock.
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Product overview
5.7.3
Multipurpose and PWM timers
STM8A devices described in this datasheet, contain up to three 16-bit multipurpose and PWM timers providing nine CAPCOM channels in total. Table 4.
Timer Timer1 Timer2 Timer3 Timer4 8 16
STM8A timer configuration
Counter Prescaler 16 15-bit fixed power of 2 ratios Up 7-bit fixed power of 2 ratios Type Up/down CAPCOM 4 3 2 0 0 No Complementary Synchronization outputs module 3 Yes
Timer 1: Multipurpose PWM timer
This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver.

16-bit up, down and up/down AR (auto-reload) counter with 16-bit prescaler Four independent CAPCOM channels configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output Trigger module which allows the interaction of timer 1 with other timers or the ADC to be controlled Break input to force the timer outputs into a defined state Three complementary outputs with adjustable dead time Interrupt sources: 4 x input capture/output compare, 1 x overflow/update, 1 x break
Timer 2 and 3: 16-bit PWM timers

16-bit auto-reload up-counter 15-bit prescaler adjustable to fixed power of two ratios 1...32768 Timers with three or two individually configurable CAPCOM channels Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
5.7.4
Timer 4: System timer

8-bit auto-reload, adjustable prescaler ratio to any power of two from 1 to 128 Clock source: master clock Interrupt source: 1 x overflow/update
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5.8
ADC
The STM8A products described in this datasheet, contain a 10-bit successive approximation ADC with 16 multiplexed input channels. General features:

10-bit ADC with up to 16 channels Input voltage range: 0 to VDDA Acqusition modes - - - Single conversion Continous acquisition - up to 100 ksamples/s effective sampling rate Trigger register and external trigger input End of conversion (EOC) - can be masked
Interrupts -
5.9
Communication interfaces
The following communication interfaces are implemented on STM8A products:

USART: Full feature UART, SPI emulation, LIN master capability LINUART: LIN2.1 master/slave capability, full feature UART SPI - full and half-duplex, 10 Mbit/s IC - up to 400 Kbit/s CAN (rev. 2.0A,B) - 3 Tx mailboxes - up to 1 Mbit/s SWIM for debugging and device programming
5.9.1
USART
Main features

1 Mbit/s full duplex SCI LIN master capable SPI emulation 16-bit baud-rate prescaler
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Product overview
Full duplex, asynchronous communication

NRZ standard format (mark/space) High-precision baud rate generator system - Common programmable transmit and receive baud rates up to 2.5 M baud Programmable data word length (8 or 9 bits) Configurable stop bits providing support for 1 or 2 stop bits LIN master mode - - LIN break and delimiter generation LIN break and delimiter detection with separate flag and interrupt source for readback checking

Transmitter clock output for synchronous communication Single wire half duplex communication Separate enable bits for transmitter and receiver Transfer detection flags - - - Receive buffer full Transmit buffer empty End of transmission flags Transmit parity bit Check parity of received data byte Overrun error Noise error Frame error Parity error Transmit data register empty Transmission complete Receive data register full Idle line received Parity error LIN break and delimiter detection Transmitter interrupt Receiver interrupt
Parity control: - -
Four error detection flags - - - -
Six interrupt sources with flags - - - - - -
Two interrupt vectors - -

Reduced power consumption mode Multi-processor communication, allowing entry into mute mode if address match does not occur Wakeup from mute mode (by idle line detection or address mark detection) Two receiver wakeup modes: - - Address bit (MSB) Idle line
21/100
Product overview
STM8AF61xx, STM8AF51xx
5.9.2
LINUART
Main features

LIN master/slave rev. 2.1 compliant Auto-synchronization in LIN slave mode 16-bit baud rate prescaler 1 Mbit full duplex SCI
LIN master

Autonomous header handling 13-bit LIN synch break generation
LIN slave

Autonomous header handling - one single interrupt per valid message header Automatic baud rate synchronization - maximum tolerated initial clock deviation 15 % Synch delimiter checking 11-bit LIN synch break detection - break detection always active Parity check on the LIN identifier field LIN error management Hot plugging support
Asynchronous communication (UART)

Full duplex, asynchronous communications - NRZ standard format (mark/space) Independently programmable transmit and receive baud rates up to 500 Kbit/s Programmable data word length (8 or 9 bits) Low-power standby mode - two receiver wake-up modes: - - Address bit (MSB) Idle line

Muting function for multiprocessor configurations Overrun, noise and frame error detection Six interrupt sources Tx, Rx parity control
5.9.3
SPI

Maximum speed: 10 Mbit/s or fCPU/2 both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on two lines with a possible bidirectional data line Master or slave operation - selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave/master selection input pin
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STM8AF61xx, STM8AF51xx
Product overview
5.9.4
I2C
I2C master features: - - Clock generation Start and stop generation slave features: Programmable I2C address detection Stop bit detection
I2C - -

Generation and detection of 7-bit/10-bit addressing and general call Supports different communication speeds: - - Standard speed (up to 100 kHz), Fast speed (up to 400 kHz) Successful address/data communication Error condition Wake-up from halt
Interrupt: - - -
Wake-up from halt on address detection in slave mode
5.9.5
CAN
The beCAN3 controller (basic enhanced CAN), interfaces the CAN network and supports the CAN protocol version 2.0A and B. It has been designed to manage a high number of incoming messages efficiently with a minimum CPU load. For safety-critical applications, the CAN controller provides all hardware functions to support the CAN time triggered communication option (TTCAN). The maximum transmission speed is 1 Mbit.
Transmission

Three transmit mailboxes Configurable transmit priority by identifier or order request Time stamp on SOF transmission
Reception

11- and 29-bit ID 1 receive FIFO (3 messages deep) Software-efficient mailbox mapping at a unique address space FMI (filter match index) stored with message Configurable FIFO overrun Time stamp on SOF reception 6 filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID
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Product overview
STM8AF61xx, STM8AF51xx
Filtering modes: - - Mask mode permitting ID range filtering ID list mode Disable automatic retransmission mode 16-bit free running timer Configurable timer resolution Time stamp sent in last two data bytes
Time triggered communication option - - - -
Interrupt management

Maskable interrupt Software-efficient mailbox mapping at a unique address space
5.10
Input/output specifications
The product features four different I/O types:

Standard I/O 2 MHz Fast I/O 10 MHz High sink 8 mA, 2 MHz True open drain (I2C interface)
To decrease EMI (electromagnetic interference), high sink I/Os have a limited maximum slew rate. The rise and fall times are similar to those of standard I/Os. Selected I/Os include a low leakage analog switch. STM8A I/Os are designed to withstand current injection. For a negative injection current of 4 mA, the resulting leakage current in the adjacent input does not exceed 1 A. External protection diodes are no longer required.
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STM8AF61xx, STM8AF51xx
Pinouts and pin description
6
6.1
Pinouts and pin description
Package pinouts
Figure 3. LQFP 80-pin pinout
PD7/TLI PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CC1/BEEP PD3 (HS)/TIM2_CC2 PD2 (HS)/TIM3_CC1 PD1 (HS)/SWIM PD0 (HS)/TIM3_CC2 PI7 PI6 PE0/CLK_CCO PE1/I2C_SCL PE2/I 2C_SDA PE3/TIM1_BKIN PE4 PG7 PG6 PG5 PI5 PI4 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 TIM2_CC3/PA3 USART_RX/PA4 USART_TX/PA5 USART_CK/PA6 (HS) PH0 (HS) PH1 PH2 PH3 AIN15/PF7 AIN14/PF6 AIN13/PF5 AIN12/PF4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PI3 PI2 PI1 PI0 PG4 PG3 PG2 PG1/CAN_RX(1) PG0/CAN_TX(1) PC7/SPI_MISO PC6/SPI_MOSI VDDIO_2 VSSIO_2 PC5/SPI_SCK PC4 (HS)/TIM1_CC4 PC3 (HS)/TIM1_CC3 PC2 (HS)/TIM1_CC2 PC1 (HS)/TIM1_CC1 PC0/ADC_ETR PE5/SPI_NSS
AIN11/PF3 VREF+ VDDA VSSA VREFAIN10/PF0 AIN7/PB7 AIN6/PB6 AIN5/PB5 AIN4/PB4 AIN3/PB3 AIN2/PB2 AIN1/PB1 AIN0/PB0 TIM1_ETR/PH4 TIM1_NCC3/PH5 TIM1_NCC2/PH6 TIM1_NCC1/PH7 AIN8/PE7 AIN9/PE6
(HS) high sink capability
1. The CAN interface is only available on the STM8AF/H51xx product line
25/100
Pinouts and pin description Figure 4. LQFP 64-pin pinout
PD7/TLI PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CC1/ BEEP PD3 (HS)/TIM2_CC2/ADC_ETR PD2 (HS)/TIM3_CC1 PD1 (HS)/SWIM PD0 (HS)/TIM3_CC2 PE0/CLK_CCO PE1/I2C_SCL PE2/I2C_SDA PE3/TIM1_BKIN PE4 PG7 PG6 PG5 NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 TIM2_CC3/PA3 USART_RX/PA4 USART_TX/PA5 USART_CK/PA6 AIN15/PF7 AIN14/PF6 AIN13/PF5 AIN12/PF4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AIN11/PF3 VREF+ VDDA VSSA VREFAIN10/PF0 AIN7/PB7 AIN6/PB6 AIN5/PB5 AIN4/PB4 TIM1_ETR/AIN3/PB3 TIM1_NCC3/AIN2/PB2 TIM1_NCC2/AIN1/PB1 TIM1_NCC1/AIN0/PB0 AIN8/PE7 AIN9/PE6
STM8AF61xx, STM8AF51xx
PI0 PG4 PG3 PG2 PG1/CAN_RX(1) PG0/CAN_TX(1) PC7/SPI_MISO PC6/SPI_MOSI VDDIO_2 VSSIO_2 PC5/SPI_SCK PC4 (HS)/TIM1_CC4 PC3 (HS)/TIM1_CC3 PC2 (HS)/TIM1_CC2 PC1 (HS)/TIM1_CC1 PE5/SPI_NSS
(HS) high sink capability
1. The CAN interface is only available on the STM8AF/H51xx product line
26/100
STM8AF61xx, STM8AF51xx Figure 5. LQFP 48-pin pinout
PD7/TLI PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CC1/BEEP PD3 (HS)/TIM2_CC2/ADC_ETR PD2 (HS)/TIM3_CC1 PD1 (HS)/SWIM PD0 (HS)/TIM3_CC2 PE0/CLK_CCO PE1/I2C_SCL PE2/I2C_SDA PE3/TIM1_BKIN
Pinouts and pin description
NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 TIM2_CC3/PA3 PA4 PA5 PA6
48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 2223 24 VDDA VSSA AIN7/PB7 AIN6/PB6 AIN5/PB5 AIN4/PB4 TIM1_ETR/AIN3/PB3 TIM1_NCC3/AIN2/PB2 TIM1_NCC2/AIN1/PB1 TIM1_NCC1/AIN0/PB0 AIN8/PE7 AIN9/PE6
PG1 PG0 PC7/SPI_MISO PC6/SPI_MOSI VDDIO_2 VSSIO_2 PC5/SPI_SCK PC4 (HS)/TIM1_CC4 PC3 (HS)/TIM1_CC3 PC2 (HS)/TIM1_CC2 PC1 (HS)/TIM1_CC1 PE5/SPI_NSS
(HS) high sink capability
1. The CAN interface is only available on the STM8AF/H51xx product line
27/100
Pinouts and pin description Figure 6. LQFP 32-pin pinout
PD7/TLI PD6/LINUART_RX PD5/LINUART_TX PD4 (HS)/TIM2_CC1/BEEP PD3 (HS)/TIM2_CC2/ADC_ETR PD2 (HS)/TIM3_CC1/TIM2_CC3 PD1 (HS)/SWIM PD0 (HS)/TIM3_CC2/CLK_CCO/TIM1_BRK
STM8AF61xx, STM8AF51xx
NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD VDDIO AIN12/PF4
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 1516 VDDA VSSA I2C_SDA/AIN5/PB5 I2C_SCL/AIN4/PB4 TIM1_ETR/AIN3/PB3 TIM1_NCC3/AIN2/PB2 TIM1_NCC2/AIN1/PB1 TIM1_NCC1/AIN0/PB0
PC7/SPI_MISO PC6/SPI_MOSI PC5/SPI_SCK PC4 (HS)/TIM1_CC4 PC3 (HS)/TIM1_CC3 PC2 (HS)/TIM1_CC2 PC1 (HS)/TIM1_CC1 PE5/SPI_NSS
(HS) high sink capability
6.2
Pin description
Table 5.
Type Level
Legend/abbreviation for Table 6
I= input, O = output, S = power supply Input Output CM = CMOS (standard for all I/Os) HS = High sink (8 mA)
Output speed
O1 = Standard (up to 2 MHz) O2 = Fast (up to 10 MHz) O3 = Fast/slow programmability with slow as default state after reset O4 = Fast/slow programmability with fast as default state after reset float = floating, wpu = weak pull-up T = true open drain, OD = open drain, PP = push pull
Port and control Input configuration Output
Reset state is shown in bold.
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STM8AF61xx, STM8AF51xx Table 6. STM8A microcontroller family pin description
Input Ext. interrupt Type High sink floating Output
Pinouts and pin description
Pin number LQFP80 LQFP64 LQFP48 LQFP32
Speed
wpu
OD
Pin name
Main function Default alternate (after function reset)
Alternate function after remap [option bit]
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9
1 NRST 2 PA1/OSCIN 3 PA2/OSCOUT - VSSIO_1 4 VSS 5 VCAP 6 VDD 7 VDDIO_1 - PA3/TIM2_CC3 - PA4/USART_RX - PA5/USART_TX - PA6/USART_CK - PH0 - PH1 - PH2 - PH3 - PF7/AIN15 - PF6/AIN14 - PF5/AIN13 8 PF4/AIN12 - PF3/AIN11 - VREF+ 9 VDDA
I/O I/O X I/O X S S S S S I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X S S S S I/O X
X X X X O1 O1 X X
PP
Reset X Port A1 X Port A2 Resonator/crystal in Resonator/crystal out
I/O ground Digital ground 1.8 V regulator capacitor Digital power supply I/O power supply X X X X X X X X X X X X X X X X X O1 O3 O3 O3 HS O3 HS O3 O1 O1 O1 O1 O1 O1 O1 X X X X X X X X X X X X X X Port A3 Timer 2 channel3 TIM3_CC1 [AFR1]
10 10 10 11 11 11 12 12 12 13 14 15 16 -
X Port A4 USART receive X Port A5 USART transmit USART X Port A6 synchronous clock X Port H0 X Port H1 X Port H2 X Port H3 X Port F7 X Port F6 X Port F5 X Port F4 X Port F3 Analog input 15 Analog input 14 Analog input 13 Analog input 12 Analog input 11
17 13 18 14 19 15 20 16 21 17 22 18
ADC positive reference voltage Analog power supply Analog ground ADC negative reference voltage X O1 X X Port F0 Analog input 10
23 19 13
24 20 14 10 VSSA 25 21 26 22 - VREF- PF0/AIN10
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Pinouts and pin description Table 6. STM8A microcontroller family pin description (continued)
Input Ext. interrupt Type High sink floating Output
STM8AF61xx, STM8AF51xx
Pin number LQFP80 LQFP64 LQFP48 LQFP32
Speed
wpu
OD
Pin name
Main function Default alternate (after function reset)
Alternate function after remap [option bit]
27 23 15 28 24 16
- PB7/AIN7 - PB6/AIN6
I/O X I/O X I/O X I/O X I/O X
X X X X X
X X X X X
O1 O1 O1 O1 O1
X X X X X
X Port B7 Analog input 7 X Port B6 Analog input 6 X Port B5 Analog input 5 X Port B4 Analog input 4 X Port B3 Analog input 3 I2C_SDA [AFR6] I2C_SCL [AFR6] TIM1_ETR [AFR5] TIM1_ NCC3 [AFR5] TIM1_ NCC2 [AFR5] TIM1_ NCC1 [AFR5]
29 25 17 11 PB5/AIN5 30 26 18 12 PB4/AIN4 31 27 19 13 PB3/AIN3
32 28 20 14 PB2/AIN2
I/O X
X
X
O1
X
X Port B2 Analog input
33 29 21 15 PB1/AIN1
I/O X
X
X
O1
X
X Port B1 Analog input 1
34 30 22 16 PB0/AIN0
I/O X
X
X
O1
X
X Port B0 Analog input 0 Timer 1 - trigger input Timer 1 - inverted channel 3 Timer 1 - inverted channel 2 Timer 1 - inverted channel 2 Analog input 8 Analog input 9 SPI master/slave select
35 36 37 38
-
-
- PH4/TIM1_ETR
I/O X
X X X X X X X X X X X X X X X X X
O1 O1 O1 O1 O1 O1 O1 O1 HS O3 HS O3 HS O3
X X X X X X X X X X X
X Port H4 X Port H5 X Port H6 X Port H7 X Port E7 X Port E7 X Port E5
- PH5/ TIM1_NCC3 I/O X - PH6/TIM1_NCC2 I/O X - PH7/TIM1_NCC1 I/O X - PE7/AIN8 PE6/AIN9 I/O X I/O X I/O X I/O X I/O X I/O X I/O X
39 31 23 40 32 24
41 33 25 17 PE5/SPI_NSS 42 - PC0/ADC_ETR
X Port C0 ADC trigger input X Port C1 X Port C2 X Port C3 Timer 1 - channel 1 Timer 1- channel 2 Timer 1 - channel 3
43 34 26 18 PC1/TIM1_CC1 44 35 27 19 PC2/TIM1_CC2 45 36 28 20 PC3/TIM1_CC3
30/100
PP
STM8AF61xx, STM8AF51xx Table 6.
Pinouts and pin description
STM8A microcontroller family pin description (continued)
Input Ext. interrupt Type High sink floating Output Main function Default alternate (after function reset) Alternate function after remap [option bit]
Pin number LQFP80 LQFP64 LQFP48 LQFP32
Speed
wpu
OD
Pin name
PP
46 37 29 21 PC4/TIM1_CC4 47 38 30 22 PC5/SPI_SCK 48 39 31 49 40 32 - VSSIO_2 - VDDIO_2
I/O X I/O X S S I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X
X X
X X
HS O3 O3
X X
X Port C4
Timer 1 - channel 4
X Port C5 SPI clock I/O ground I/O power supply
50 41 33 23 PC6/SPI_MOSI 51 42 34 24 PC7/SPI_MISO 52 43 35 53 44 36 54 45 55 46 56 47 57 48 58 59 60 61 62 - PG0/CAN_TX - PG1/CAN_RX - PG2 - PG3 - PG4 - PI0 - PI1 - PI2 - PI3 - PI4 - PI5 - PG5 - PG6 - PG7 - PE4 - PE3/TIM1_BKIN - PE2/I2C_SDA - PE1/I2C_SCL - PE0/CLK_CCO - PI6 - PI7
X X X X X X X X X X X X X X X X X X X X X X X
X X
O3 O3 O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 O1 O1
X X X X X X X X X X X X X X X X X X
X Port C6 X Port C7
SPI master out/ slave in SPI master in/ slave out
X Port G0 CAN transmit X Port G1 CAN receive X Port G2 X Port G3 X Port G4 X Port I0 X Port I1 X Port I2 X Port I3 X Port I4 X Port I5 X Port G5 X Port G6 X Port G7 X Port E4 X Port E3 Timer 1 - break input I2C data I2C clock Configurable clock output
63 49 64 50 65 51 66 52
X X X X X
O1 O1
67 53 37 68 54 38 69 55 39 70 56 40 71 72 -
O1 T(1) X Port E2 O1 T(1) X Port E1 O3 O1 O1 X X X X Port E0 X Port I6 X Port I7
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Pinouts and pin description Table 6. STM8A microcontroller family pin description (continued)
Input Ext. interrupt Type High sink floating Output
STM8AF61xx, STM8AF51xx
Pin number LQFP80 LQFP64 LQFP48 LQFP32
Speed
wpu
OD
Pin name
Main function Default alternate (after function reset)
Alternate function after remap [option bit]
73 57 41 25 PD0/TIM3_CC2
I/O X
X
X
HS O3
X
TIM1_BKIN Timer 3 - channel [AFR3]/ X Port D0 2 CLK_CCO [AFR2] X Port D1 X Port D2 X Port D3 SWIM data interface Timer 3 - channel TIM2_CC3 1 [AFR1] Timer 2 - channel ADC_ETR 2 [AFR0] BEEP Timer 2 - channel output 1 [AFR7] LINUART data transmit LINUART data receive
74 58 42 26 PD1/SWIM 75 59 43 27 PD2/TIM3_CC1 76 60 44 28 PD3/TIM2_CC2
I/O X I/O X I/O X
X X X
X X X
HS O4 HS O3 HS O3
X X X
77 61 45 29
PD4/TIM2_CC1/B I/O X EEP PD5/ LINUART_TX I/O X
X
X
HS O3
X
X Port D4
78 62 46 30
X
X
O1
X
X Port D5 Port D6
79 63 47 31
PD6/ LINUART_RX
I/O X
X
X
O1
X
X Caution: This pin must be held low during power on
PP
80 64 48 32 PD7/TLI
I/O X
X
X
O1
X
X Port D7 Top level interrupt
TIM1_CC4 [AFR4]
1. In the open-drain output column, `T' defines a true open-drain I/O (P-buffer and protection diode to VDD are not implemented)
6.2.1
Alternate function remapping
As shown in the rightmost column of Table 6, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to Section 10: Option bytes on page 49. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the STM8A microcontroller family reference manual, RM0009).
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STM8AF61xx, STM8AF51xx
Memory map
7
Memory map
Figure 7. Register and memory map
00 0000 Up to 6 Kbytes RAM Up to 1 Kbyte stack Reserved 00 4000 00 4800 Option and engineering bytes 00 4900 00 5000 00 5800 Reserved 00 6000 2 Kbytes ROM 00 6800 00 7F00 CPU registers 00 8000 IT vectors 00 8080 Reserved HW registers Up to 2 Kbytes data EEPROM
00 1800
Up to 128 Kbytes code Flash
02 7FFF
Table 7.
Product Kbytes 128
Stack and RAM partitioning
RAM size Kbytes 6 Stack size RAM end Dec 17FF 1024 Hex 0400 1400 Stack start
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Interrupt table
STM8AF61xx, STM8AF51xx
8
Interrupt table
Table 8.
Priority 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
STM8A interrupt table
Source block Reset TRAP TLI AWU Clock controller MISC MISC MISC MISC MISC CAN CAN SPI Timer 1 Timer 1 Timer 2 Timer 2 Timer 3 Timer 3 USART (SCI1) USART (SCI1) I2C LINUART (SCI2) LINUART (SCI2) Description Reset SW interrupt External top level interrupt Auto wake up from halt Main clock controller Ext interrupt E0 Ext interrupt E1 Ext interrupt E2 Ext interrupt E3 Ext interrupt E4 CAN interrupt Rx CAN interrupt TX/ER/SC End of transfer Update/overflow/ trigger/break Capture/compare Update/overflow/ break Capture/compare Update/overflow/ break Capture/compare Tx complete/ ER/SPI EOT/SPI error Receive data full reg. I2C interrupts Tx complete/error/ SPI EOT/SPI error Receive data full reg. Interrupt vector Wake-up address from halt 6000h 8004h 8008h 800Ch 8010h 8014h 8018h 801Ch 8020h 8024h 8028h 802Ch 8030h 8034h 8038h 803Ch 8040h 8044h 8048h 804Ch Trigger not available on medium end timer Trigger not available on medium end timer Yes Yes Yes Yes Yes Yes Yes Port A interrupts Port B interrupts Port C interrupts Port D interrupts Port E interrupts Yes Yes Comments Reset vector in ROM
18 19 20 21
8050h 8054h 8058h 805Ch Yes
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STM8AF61xx, STM8AF51xx Table 8.
Priority 22 23 24
Interrupt table
STM8A interrupt table (continued)
Source block ADC Timer 4 Reserved(1) Description End of conversion Update/overflow Reserved Interrupt vector Wake-up address from halt 8060h 8064h 8068h Comments
1. Also unused interrupts should be initialised with "IRET" for robust programming.
35/100
Register mapping
STM8AF61xx, STM8AF51xx
9
Register mapping
Table 9.
Address 00 5000h 00 5001h 00 5002h 00 5003h 00 5004h 00 5005h 00 5006h 00 5007h 00 5008h 00 5009h 00 500Ah 00 500Bh 00 500Ch 00 500Dh 00 500Eh 00 500Fh 00 5010h 00 5011h 00 5012h 00 5013h 00 5014h 00 5015h 00 5016h 00 5017h 00 5018h 00 5019h 00 501Ah 00 501Bh 00 501Ch 00 501Dh Port F Port E Port D Port C Port B Port A
STM8A I/O port hardware register map
Block Register label PA_ODR PA_IDR PA_DDR PA_CR1 PA_CR2 PB_ODR PB_IDR PB_DDR PB_CR1 PB_CR2 PC_ODR PC_IDR PC_DDR PC_CR1 PC_CR2 PD_ODR PD_IDR PD_DDR PD_CR1 PD_CR2 PE_ODR PE_IDR PE_DDR PE_CR1 PE_CR2 PF_ODR PF_IDR PF_DDR PF_CR1 PF_CR2 Register name Port A data output latch register Port A input pin value register Port A data direction register Port A control register 1 Port A control register 2 Port B data output latch register Port B input pin value register Port B data direction register Port B control register 1 Port B control register 2 Port C data output latch register Port C input pin value register Port C data direction register Port C control register 1 Port C control register 2 Port D data output latch register Port D input pin value register Port D data direction register Port D control register 1 Port D control register 2 Port E data output latch register Port E input pin value register Port E data direction register Port E control register 1 Port E control register 2 Port F data output latch register Port F input pin value register Port F data direction register Port F control register 1 Port F control register 2 Reset status 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
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STM8AF61xx, STM8AF51xx Table 9.
Address 00 501Eh 00 501Fh 00 5020h 00 5021h 00 5022h 00 5023h 00 5024h 00 5025h 00 5026h 00 5027h 00 5028h 00 5029h 00 502Ah 00 502Bh 00 502Ch Port I Port H Port G
Register mapping
STM8A I/O port hardware register map (continued)
Block Register label PG_ODR PG_IDR PG_DDR PG_CR1 PG_CR2 PH_ODR PH_IDR PH_DDR PH_CR1 PH_CR2 PI_ODR PI_IDR PI_DDR PI_CR1 PI_CR2 Register name Port G data output latch register Port G input pin value register Port G data direction register Port G control register 1 Port G control register 2 Port H data output latch register Port H input pin value register Port H data direction register Port H control register 1 Port H control register 2 Port I data output latch register Port I input pin value register Port I data direction register Port I control register 1 Port I control register 2 Reset status 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
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Register mapping Table 10.
Address 00 5050h to 00 5059h 00 505Ah 00 505Bh 00 505Ch 00 505Dh 00 505Eh 00 505Fh 00 5060h to 00 5061h 00 5062h 00 5063h 00 5064h 00 5065h to 00 509Fh 00 50A0h ITC 00 50A1h 00 50A2h to 00 50B2h 00 50B3h 00 50B4h to 00 50BFh 00 50C0h CLK 00 50C1h 00 50C2h CLK_ECKR CLK_ICKR RST RST_SR EXTI_CR2 EXTI_CR1 Flash FLASH _DUKR Flash FLASH _PUKR Flash FLASH_CR1 FLASH_CR2 FLASH_NCR2 FLASH _FPR FLASH _NFPR FLASH _IAPSR
STM8AF61xx, STM8AF51xx STM8A general hardware register map
Block Register label Register name Reset status
Reserved area (10 bytes) Flash control register 1 Flash control register 2 Flash complementary control register 2 Flash protection register Flash complementary protection register Flash in-application programming status register Reserved area (2 bytes) Flash program memory unprotection register Reserved area (1 byte) Data EEPROM unprotection register 00h 00h 00h FFh 00h FFh 00h
00h
Reserved area (59 bytes) External interrupt control register 1 External interrupt control register 2 Reserved area (17 bytes) Reset status register Reserved area (12 bytes) Internal clock control register External clock control register Reserved area (1 byte) 01h 00h xxh 00h 00h
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STM8AF61xx, STM8AF51xx Table 10.
Address 00 50C3h 00 50C4h 00 50C5h 00 50C6h 00 50C7h 00 50C8h 00 50C9h 00 50CAh 00 50CBh 00 50CCh 00 50CDh 00 50CEh to 00 50D0h 00 50D1h WWDG 00 50D2h 00 50D3h to 00 50DFh 00 50E0h 00 50E1h 00 50E2h 00 50E3h to 00 50EFh 00 50F0h 00 50F1h 00 50F2h 00 50F3h 00 50F4h to 00 50FFh BEEP AWU AWU_CSR1 AWU_APR AWU_TBR BEEP_CSR IWDG IWDG_KR IWDG_PR IWDG_RLR WWDG_WR WWDG_CR CLK
Register mapping
STM8A general hardware register map (continued)
Block Register label CLK_CMSR CLK_SWR CLK_SWCR CLK_CKDIVR CLK_PCKENR1 CLK_CSSR CLK_CCOR CLK_PCKENR2 CLK_CANCCR CLK_HSITRIMR CLK_SWIMCCR Register name Clock master status register Clock master switch register Clock switch control register Clock divider register Peripheral clock gating register 1 Clock security system register Configurable clock control register Peripheral clock gating register 2 CAN clock control register HSI clock calibration trimming register SWIM clock control register Reserved area (3 bytes) WWDG control register WWDR window register Reserved area (13 bytes) IWDG key register IWDG prescaler register IWDG reload register Reserved area (13 bytes) AWU control/status register 1 AWU asynchronous prescaler buffer register AWU timebase selection register BEEP control/status register Reserved area (12 bytes) 00h 3Fh 00h 1Fh 00h FFh 7Fh 7Fh Reset status E1h E1h xxxx 0000b 18h FFh 00h 00h FFh 00h xxh x0h
39/100
Register mapping Table 10.
Address 00 5200h 00 5201h 00 5202h 00 5203h SPI 00 5204h 00 5205h 00 5206h 00 5207h 00 5208h to 00 520Fh 00 5210h 00 5211h 00 5212h 00 5213h 00 5214h 00 5215h 00 5216h 00 5217h 00 5218h 00 5219h 00 521Ah 00 521Bh 00 521Ch 00 521Dh 00 521Eh 00 521Fh to 00 522Fh I2C I2C_DR I2C_SR1 I2C_SR2 I2C_SR3 I2C_ITR I2C_CCRL I2C_CCRH I2C_TRISER I2C_PECR I
2C
STM8AF61xx, STM8AF51xx STM8A general hardware register map (continued)
Block Register label SPI_CR1 SPI_CR2 SPI_ICR SPI_SR SPI_DR SPI_CRCPR SPI_RXCRCR SPI_TXCRCR Register name SPI control register 1 SPI control register 2 SPI interrupt control register SPI status register SPI data register SPI CRC polynomial register SPI Rx CRC register SPI Tx CRC register Reserved area (8 bytes) I2C_CR1 I2C_CR2 I2C_FREQR I2C_OARL I2C_OARH I I2C control register 1 I
2C
Reset status 00h 00h 00h 02h 00h 07h FFh FFh
00h 00h 00h 00h 00h
control register 2 frequency register
2C
I2C own address register low I
2C
own address register high Reserved I2C data register I2C status register 1 I
2C
00h 00h 00h 00h 00h 00h 00h 02h 00h
status register 2 status register 3
I2C I
2C
interrupt control register
I2C clock control register low I2C clock control register high I C TRISE register packet error checking register
2
Reserved area (17 bytes)
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STM8AF61xx, STM8AF51xx Table 10.
Address 00 5230h 00 5231h 00 5232h 00 5233h 00 5234h 00 5235h 00 5236h 00 5237h 00 5238h 00 5239h 00 523Ah 00 523Bh to 00 523Fh 00 5240h 00 5241h 00 5242h 00 5243h 00 5244h 00 5245h LINUART 00 5246h 005247h 00 5248h 00 5249h 00 524Ah to 00 524Fh LINUART_CR6 LINUART_CR3 LINUART_CR4 LINUART_SR LINUART_DR LINUART_BRR1 LINUART_BRR2 LINUART_CR1 LINUART_CR2 USART
Register mapping
STM8A general hardware register map (continued)
Block Register label USART_SR USART_DR USART_BRR1 USART_BRR2 USART_CR1 USART_CR2 USART_CR3 USART_CR4 USART_CR5 USART_GTR USART_PSCR Register name USART status register USART data register USART baud rate register 1 USART baud rate register 2 USART control register 1 USART control register 2 USART control register 3 USART control register 4 USART control register 5 USART guard time register USART prescaler register Reserved area (5 bytes) LINUART status register LINUART data register LINUART baud rate register 1 LINUART baud rate register 2 LINUART control register 1 LINUART control register 2 LINUART control register 3 LINUART control register 4 Reserved LINUART control register 6 Reserved area (6 bytes) 00h C0h xxh 00h 00h 00h 00h 00h 00h Reset status C0h xxh 00h 00h 00h 00h 00h 00h 00h 00h 00h
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Register mapping Table 10.
Address 00 5250h 00 5251h 00 5252h 00 5253h 00 5254h 00 5255h 00 5256h 00 5257h 00 5258h 00 5259h 00 525Ah 00 525Bh 00 525Ch 00 525Dh 00 525Eh 00 525Fh TIM1 00 5260h 00 5261h 00 5262h 00 5263h 00 5264h 00 5265h 00 5266h 00 5267h 00 5268h 00 5269h 00 526Ah 00 526Bh 00 526Ch 00 526Dh 00 526Eh 00 526Fh 00 5270h to 00 52FFh TIM1_PSCRH TIM1_PSCRL TIM1_ARRH TIM1_ARRL TIM1_RCR TIM1_CCR1H TIM1_CCR1L TIM1_CCR2H TIM1_CCR2L TIM1_CCR3H TIM1_CCR3L TIM1_CCR4H TIM1_CCR4L TIM1_BKR TIM1_DTR TIM1_OISR
STM8AF61xx, STM8AF51xx STM8A general hardware register map (continued)
Block Register label TIM1_CR1 TIM1_CR2 TIM1_SMCR TIM1_ETR TIM1_IER TIM1_SR1 TIM1_SR2 TIM1_EGR TIM1_CCMR1 TIM1_CCMR2 TIM1_CCMR3 TIM1_CCMR4 TIM1_CCER1 TIM1_CCER2 TIM1_CNTRH TIM1_CNTRL Register name TIM1 control register 1 TIM1 control register 2 TIM1 slave mode control register TIM1 external trigger register TIM1 interrupt enable register TIM1 status register 1 TIM1 status register 2 TIM1 event generation register TIM1 capture/compare mode register 1 TIM1 capture/compare mode register 2 TIM1 capture/compare mode register 3 TIM1 capture/compare mode register 4 TIM1 capture/compare enable register 1 TIM1 capture/compare enable register 2 TIM1 counter high TIM1 counter low TIM1 prescaler register high TIM1 prescaler register low TIM1 auto-reload register high TIM1 auto-reload register low TIM1 repetition counter register TIM1 capture/compare register 1 high TIM1 capture/compare register 1 low TIM1 capture/compare register 2 high TIM1 capture/compare register 2 low TIM1 capture/compare register 3 high TIM1 capture/compare register 3 low TIM1 capture/compare register 4 high TIM1 capture/compare register 4 low TIM1 break register TIM1 dead-time register TIM1 output idle state register Reserved area (147 bytes) Reset status 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
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STM8AF61xx, STM8AF51xx Table 10.
Address 00 5300h 00 5301h 00 5302h 00 5303h 00 5304h 00 5305h 00 5306h 00 5307h 00 5308h 00 5309h 00 530Ah 00 530Bh 00 530Ch 00 530Dh 00 530Eh 00 530Fh 00 5310h 00 5311h 00 5312h 00 5313h 00 5314h 00 5315h to 00 531Fh TIM2
Register mapping
STM8A general hardware register map (continued)
Block Register label TIM2_CR1 TIM2_IER TIM2_SR1 TIM2_SR2 TIM2_EGR TIM2_CCMR1 TIM2_CCMR2 TIM2_CCMR3 TIM2_CCER1 TIM2_CCER2 TIM2_CNTRH TIM2_CNTRL TIM2_PSCR TIM2_ARRH TIM2_ARRL TIM2_CCR1H TIM2_CCR1L TIM2_CCR2H TIM2_CCR2L TIM2_CCR3H TIM2_CCR3L Register name TIM2 control register 1 TIM2 interrupt enable register TIM2 status register 1 TIM2 status register 2 TIM2 event generation register TIM2 capture/compare mode register 1 TIM2 capture/compare mode register 2 TIM2 capture/compare mode register 3 TIM2 capture/compare enable register 1 TIM2 capture/compare enable register 2 TIM2 counter high TIM2 counter low TIM2 prescaler register TIM2 auto-reload register high TIM2 auto-reload register low TIM2 capture/compare register 1 high TIM2 capture/compare register 1 low TIM2 capture/compare register 2 high TIM2 capture/compare register 2 low TIM2 capture/compare register 3 high TIM2 capture/compare register 3 low Reserved area (11 bytes) Reset status 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h
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Register mapping Table 10.
Address 00 5320h 00 5321h 00 5322h 00 5323h 00 5324h 00 5325h 00 5326h 00 5327h 00 5328h 00 5329h 00 532Ah 00 532Bh 00 532Ch 00 532Dh 00 532Eh 00 532Fh 00 5330h 00 5331h to 00 533Fh 00 5340h 00 5341h 00 5342h 00 5343h 00 5344h 00 5345h 00 5346h 00 5347h to 00 53FFh TIM4 TIM4_CR1 TIM4_IER TIM4_SR TIM4_EGR TIM4_CNTR TIM4_PSCR TIM4_ARR TIM3
STM8AF61xx, STM8AF51xx STM8A general hardware register map (continued)
Block Register label TIM3_CR1 TIM3_IER TIM3_SR1 TIM3_SR2 TIM3_EGR TIM3_CCMR1 TIM3_CCMR2 TIM3_CCER1 TIM3_CNTRH TIM3_CNTRL TIM3_PSCR TIM3_ARRH TIM3_ARRL TIM3_CCR1H TIM3_CCR1L TIM3_CCR2H TIM3_CCR2L Register name TIM3 control register 1 TIM3 interrupt enable register TIM3 status register 1 TIM3 status register 2 TIM3 event generation register TIM3 capture/compare mode register 1 TIM3 capture/compare mode register 2 TIM3 capture/compare enable register 1 TIM3 counter high TIM3 counter low TIM3 prescaler register TIM3 auto-reload register high TIM3 auto-reload register low TIM3 capture/compare register 1 high TIM3 capture/compare register 1 low TIM3 capture/compare register 2 high TIM3 capture/compare register 2 low Reserved area (15 bytes) TIM4 control register 1 TIM4 interrupt enable register TIM4 status register TIM4 event generation register TIM4 counter TIM4 prescaler register TIM4 auto-reload register Reserved area (184 bytes) 00h 00h 00h 00h 00h 00h FFh Reset status 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h FFh FFh 00h 00h 00h 00h
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STM8AF61xx, STM8AF51xx Table 10.
Address 00 5400h 00 5401h 00 5402h 00 5403h ADC 00 5404h 00 5405h 00 5406h 00 5407h 00 5408h to 00 541Fh 00 5420h 00 5421h 00 5422h 00 5423h 00 5424h 00 5425h 00 5426h 00 5427h 00 5428h 00 5429h 00 542Ah 00 542Bh CAN 00 542Ch 00 542Dh 00 542Eh 00 542Fh 00 5430h 00 5431h 00 5432h 00 5433h 00 5434h 00 5435h 00 5436h 00 5437h CAN_P4 CAN_P5 CAN_P6 CAN_P7 CAN_P8 CAN_P9 CAN_PA CAN_PB CAN_PC CAN_PD CAN_PE CAN_PF CAN paged register 4 CAN paged register 5 CAN paged register 6 CAN paged register 7 CAN paged register 8 CAN paged register 9 CAN paged register A CAN paged register B CAN_MCR CAN_MSR CAN_TSR CAN_TPR CAN_RFR CAN_IER CAN_DGR CAN_FPSR CAN_P0 CAN_P1 CAN_P2 CAN_P3 ADC_DRH ADC_DRL ADC_TDRH ADC_TDRL
Register mapping
STM8A general hardware register map (continued)
Block Register label ADC _CSR ADC_CR1 ADC_CR2 ADC_CR3 Register name ADC control/status register ADC configuration register 1 ADC configuration register 2 ADC configuration register 3 ADC data register high ADC data register low ADC Schmitt trigger disable register high ADC Schmitt trigger disable register low Reserved area (24 bytes) CAN master control register CAN master status register CAN transmit status register CAN transmit priority register CAN receive FIFO register CAN interrupt enable register CAN diagnosis register CAN page selection register CAN paged register 0 CAN paged register 1 CAN paged register 2 CAN paged register 3 02h 02h 00h 0Ch 00h 00h 0Ch 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h Reset status 00h 00h 00h 00h 00h 00h 00h 00h
CAN paged register C CAN paged register D CAN paged register E CAN paged register F
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Register mapping Table 10.
Address 00 5438h to 00 57FFh 5800h 5801h 5802h 5803h 5804h 5805h 5806h 5807h 5808h TMU
STM8AF61xx, STM8AF51xx STM8A general hardware register map (continued)
Block Register label Register name Reset status
Reserved area (968 bytes) TU_KEYS_REG0 TU_KEYS_REG1 TU_KEYS_REG2 TU_KEYS_REG3 TU_KEYS_REG4 TU_KEYS_REG5 TU_KEYS_REG6 TU_KEYS_REG7 TU_CTL_ST TMU key register 0 [7:0] TMU key register 1 [7:0] TMU key register 2 [7:0] TMU key register 3 [7:0] TMU key register 4 [7:0] TMU key register 5 [7:0]] TMU key register 6 [7:0] TMU key register 7 [7:0] TMU control and status register 00h 00h 00h 00h 00h 00h 00h 00h 00h
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STM8AF61xx, STM8AF51xx Table 11.
Address 00 7F00h 00 7F01h 00 7F02h 00 7F03h 00 7F04h 00 7F05h CPU 00 7F06h 00 7F07h 00 7F08h 00 7F09h 00 7F0Ah 00 7F0Bh to 00 7F5Fh 00 7F60h 00 7F70h 00 7F71h 00 7F72h 00 7F73h 00 7F74h 00 7F75h 00 7F76h 00 7F77h to 00 7F79h 00 7F80h 00 7F81h to 00 7F8Fh SWIM SWIM_CSR ITC CFG CFG_GCR ITC_SPR1 ITC_SPR2 ITC_SPR3 ITC_SPR4 ITC_SPR5 ITC_SPR6 ITC_SPR7 YH YL SPH SPL CCR Y index register high Y index register low Stack pointer high Stack pointer low Condition code register Reserved area (85 bytes)
Register mapping
CPU/SWIM/debug module/interrupt controller registers
Block Register label A PCE PCH PCL XH XL Register name Accumulator Program counter extended Program counter high Program counter low X index register high X index register low Reset status 00h 00h 60h 00h 00h 00h 00h 00h 17h FFh 28h
Global configuration register Interrupt software priority register 1 Interrupt software priority register 2 Interrupt software priority register 3 Interrupt software priority register 4 Interrupt software priority register 5 Interrupt software priority register 6 Interrupt software priority register 7 Reserved area (3 bytes) SWIM control status register Reserved area (15 bytes)
00h FFh FFh FFh FFh FFh FFh FFh
00h
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Register mapping Table 11.
Address 00 7F90h 00 7F91h 00 7F92h 00 7F93h 00 7F94h 00 7F95h 00 7F96h 00 7F97h 00 7F98h 00 7F99h 00 7F9Ah 00 7F9Bh to 00 7F9Fh DM
STM8AF61xx, STM8AF51xx CPU/SWIM/debug module/interrupt controller registers (continued)
Block Register label DM_BK1RE DM_BK1RH DM_BK1RL DM_BK2RE DM_BK2RH DM_BK2RL DM_CR1 DM_CR2 DM_CSR1 DM_CSR2 DM_ENFCTR Register name DM breakpoint 1 register extended byte DM breakpoint 1 register high byte DM breakpoint 1 register low byte DM breakpoint 2 register extended byte DM breakpoint 2 register high byte DM breakpoint 2 register low byte Debug module control register 1 Debug module control register 2 Debug module control/status register 1 Debug module control/status register 2 DM enable function register Reserved area (5 bytes) Reset status FFh FFh FFh FFh FFh FFh 00h 00h 10h 00h FFh
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STM8AF61xx, STM8AF51xx
Option bytes
10
Option bytes
Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in Table 12: Option bytes below. Option bytes can also be modified `on the fly' by the application in IAP mode, except the ROP and UBC options that can only be toggled in ICP mode (via SWIM). Refer to the STM8 Flash programming manual (PM0047) and STM8 SWIM communication protocol and debug modulel user manual (UM0470) for information on SWIM programming procedures. Table 12.
Addr.
Option bytes
Option name Option byte no. Option bits 7 6 5 4 3 ROP[7:0] UBC[7:0] NUBC[7:0] AFR7 NAFR 7 AFR6 AFR5 AFR4 NAFR4 AFR3 NAFR3 LSI _EN NLSI _EN EXT CLK NEXT CLK HSECNT[7:0] NHSECNT[7:0] TMU[0:3] NTMU[0:3] Reserved Reserved Reserved WAIT STATE NWAIT STATE AFR2 NAFR2 IWDG _HW AFR1 AFR0 2 1 0 Factory default setting 00h 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh 00h FFh
Read-out 4800h protection OPT0 (ROP) User OPT1 boot code 4802h (UBC) NOPT1 4803h Alternate function 4804h remappin g (AFR) 4805h Watchdog option 4806h 4807h Clock option 4808h 4809h HSE clock 480Ah startup 480Bh TMU 480Ch 480Dh Flash wait states 480Eh 480Fh NOPT7 NOPT6 OPT7 NOPT4 OPT5 NOPT5 OPT6 Reserved NOPT3 OPT4 Reserved Reserved OPT2 NOPT2 OPT3 4801h
NAFR NAFR5 6 Reserved
NAFR1 NAFR0 WWDG WWDG _HW _HALT
NIWDG NWWD NWWG _HW G_HW _HALT CKAWU SEL NCKAW USEL PRS C1 NPR SC1 PRS C0 NPR SC0
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Option bytes Table 12.
Addr. 4810h 4811h 4812h 4813h 4814h 4815h 4816h 4817h 4818h 4819h to 487D 487E 487F Bootloader OPT17 NOPT17 TMU
STM8AF61xx, STM8AF51xx
Option bytes (continued)
Option name Option byte no. OPT8 OPT9 OPT10 OPT11 OPT12 OPT13 OPT14 OPT15 OPT16 Option bits 7 6 5 4 3 2 1 0 Factory default setting 00h 00h 00h 00h 00h 00h 00h 00h 00h
TMU_KEY 0 [7:0] TMU_KEY 1 [7:0] TMU_KEY 2 [7:0] TMU_KEY 3 [7:0] TMU_KEY 4 [7:0] TMU_KEY 5 [7:0] TMU_KEY 6 [7:0] TMU_KEY 7 [7:0] TMU MAX_ATT [7:0] Reserved BL_EN [7:0] NBL_EN [7:0]
00h 00h
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STM8AF61xx, STM8AF51xx Table 13. Option byte description
Description
Option bytes
Option byte no.
OPT0
ROP[7:0]: Memory readout protection (ROP) AAh: Enable readout protection (write access via SWIM protocol) Note: Refer to the STM8A microcontroller family reference manual (RM0009) section on Flash/EEPROM memory readout protection for details. UBC[7:0]: User boot code area 00h: No UBC, no write-protection 01h: Page 0 to 1 defined as UBC, memory write-protected 02h: Page 0 to 3 defined as UBC, memory write-protected 03h to FFh: Pages 4 to 255 defined as UBC, memory write-protected Note: Refer to the STM8A microcontroller family reference manual (RM0009) section on Flash/EEPROM write protection for more details. AFR7: Alternate function remapping option 7 0: Port D4 alternate function = TIM2_CC1 1: Port D4 alternate function = BEEP AFR6: Alternate function remapping option 6 0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4 1: Port B5 alternate function = I2C_SDA, port B4 alternate function = I2C_SCL. AFR5: Alternate function remapping option 5 0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2, port B1 alternate function = AIN1, port B0 alternate function = AIN0. 1: Port B3 alternate function = TIM1_ETR, port B2 alternate function = TIM1_NCC3, port B1 alternate function = TIM1_NCC2, port B0 alternate function = TIM1_NCC1. AFR4: Alternate function remapping option 4 0: Port D7 alternate function = TLI 1: Port D7 alternate function = TIM1_CC4 AFR3: Alternate function remapping option 3 0: Port D0 alternate function = TIM3_CC2 1: Port D0 alternate function = TIM1_BKIN AFR2: Alternate function remapping option 2 0: Port D0 alternate function = TIM3_CC2 1: Port D0 alternate function = CLK_CCO Note: AFR2 option has priority over AFR3 if both are activated AFR1: Alternate function remapping option 1 0: Port A3 alternate function = TIM2_CC3, port D2 alternate function TIM3_CC1. 1: Port A3 alternate function = TIM3_CC1, port D2 alternate function TIM2_CC3. AFR0: Alternate function remapping option 0 0: Port D3 alternate function = TIM2_CC2 1: Port D3 alternate function = ADC_ETR
OPT1
OPT2
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Option bytes Table 13. Option byte description (continued)
STM8AF61xx, STM8AF51xx
Option byte no.
Description LSI_EN: Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source IWDG_HW: Independent watchdog 0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware
OPT3 WWDG_HW: Window watchdog activation 0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware WWDG_HALT: Window watchdog reset on halt 0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN CKAWUSEL: Auto wake-up unit/clock 0: LSI clock source selected for AWU 1: HSE clock with prescaler selected as clock source for for AWU PRSC[1:0]: AWU clock prescaler 00: 24 MHz to 128 kHz prescaler 01: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler OPT5 HSECNT[7:0]: HSE crystal oscillator stabilization time This configures the stabilisation time to 0, 16, 256, 4096 HSE cycles. TMU[3:0]: Enable temporary memory unprotection 0101: Read-out protection can be temporary disabled using a key sequence. Any other value: Permanent ROP WAIT STATE: Wait state configuration This option configures the number of wait states inserted when reading from the Flash/data EEPROM memory. 0: No wait state 1: One wait state TMU_KEY 0 [7:0]: Temporary unprotection key 0 Temporary unprotection key: Must be different from 00h or FFh TMU_KEY 1 [7:0]: Temporary unprotection key 1 Temporary unprotection key: Must be different from 00h or FFh TMU_KEY 2 [7:0]: Temporary unprotection key 2 Temporary unprotection key: Must be different from 00h or FFh TMU_KEY 3 [7:0]: Temporary unprotection key 3 Temporary unprotection key: Must be different from 00h or FFh
OPT4
OPT6
OPT7
OPT8 OPT9 OPT10 OPT11
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STM8AF61xx, STM8AF51xx Table 13. Option byte description (continued)
Description
Option bytes
Option byte no. OPT12 OPT13 OPT14 OPT15
TMU_KEY 4 [7:0]: Temporary unprotection key 4 Temporary unprotection key: Must be different from 00h or FFh TMU_KEY 5 [7:0]: Temporary unprotection key 5 Temporary unprotection key: Must be different from 00h or FFh TMU_KEY 6 [7:0]: Temporary unprotection key 6 Temporary unprotection key: Must be different from 00h or FFh TMU_KEY 7 [7:0]: Temporary unprotection key 7 Temporary unprotection key: Must be different from 00h or FFh TMU_MAXATT [7:0]: TMU access failure counter Every unsuccessful trial to enter the temporary unprotection procedure increments the counter. More than eight unsuccessful trials trigger the global erase of the code and data memory. BL_EN [7:0]: Bootloader enable If this optionbyte is set to 55h (complementary value AAh) the bootloader program is activated also in case of a programmed code memory (for more details, see the bootloader user manual, UM0500).
OPT16
OPT17
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Electrical characteristics
STM8AF61xx, STM8AF51xx
11
11.1
Electrical characteristics
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
11.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production.
11.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 C, VDD = 5.0 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range.
11.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
11.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8. Figure 8. Pin loading conditions
STM8A pin
50 pF
54/100
STM8AF61xx, STM8AF51xx
Electrical characteristics
11.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9. Figure 9. Pin input voltage
STM8A pin
VIN
11.2
Absolute maximum ratings
Stresses above those listed as `absolute maximum ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 14.
Symbol VDDx - VSS VIN
Voltage characteristics
Ratings Supply voltage (including VDDA and VDDIO)(1) Input voltage on true open drain pins (PE1, PE2)(2) Input voltage on any other pin(2) Min -0.3 VSS - 0.3 VSS - 0.3 Max 6.5 6.5 VDD + 0.3 50 mV 50 see Absolute maximum ratings (electrical sensitivity) on page 86 V Unit
|VDDx - VSS| Variations between different power pins |VSSx - VSS| Variations between all the different ground pins VESD Electrostatic discharge voltage
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external power supply 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected
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Electrical characteristics Table 15.
Symbol IVDD IVSS IIO
STM8AF61xx, STM8AF51xx
Current characteristics
Ratings Total current into VDD power lines (source)(1)(2) Total current out of VSS ground lines (sink)(1)(2) Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on NRST pin Max. 60 60 20 - 20 10 10 10 20 mA Unit
IINJ(PIN)(3)
Injected current on OSCIN pin Injected current on any other pin
IINJ(PIN)(4)
Total injected current (sum of all I/O and control pins)
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external supply. 2. The total limit applies to the sum of operation and injected currents. 3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. For true open-drain pads, there is no positive injection current allowed and the corresponding VIN maximum must always be respected. 4. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the sum of the absolute positive and negative injected currents (instantaneous values). These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 16.
Thermal characteristics
Ratings Storage temperature range Maximum junction temperature Value -65 to +150 C 150 Unit
Symbol TSTG TJ
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STM8AF61xx, STM8AF51xx
Electrical characteristics
11.3
Operating conditions
Table 17.
Symbol fCPU
General operating conditions
Parameter Internal CPU clock frequency Conditions TA 105 C TA > 105 C Min 0 0 3.0 Suffix A Suffix B -40 -40 -40 -40 -40 -40 -40 -40 Max 24 MHz 16 5.5 85 105 125 145 90 110 130 150 V C C C C C C C C Unit
VDD/VDD_IO Standard operating voltage
TA
Ambient temperature Suffix C Suffix D A suffix version B suffix version
TJ
Junction temperature range C suffix version D suffix version
Figure 10. fCPUmax versus VDD
fCPU [MHz]
24 Functionality not guaranteed in this area
16
Functionality guaranteed @ TA -40 to 105 x Functionality guaranteed @ TA -40 to 125 x
12 8 4 0 3.0
4.0
5.0
5.5
Supply voltage [V]
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Electrical characteristics Table 18.
Symbol
STM8AF61xx, STM8AF51xx
Operating conditions at power-up/power-down
Parameter VDD rise time rate Conditions Min 20(1) 20(2) VDD rising VDD falling TBD(2) TBD(2) 2.65 2.58 3 3 2.8 2.73 70(1) 2.95 2.88 Typ Max s/V Unit
tVDD
VDD fall time rate(3) Reset release delay
ms s V V mV
tTEMP
Reset generation delay(3) Power-on reset threshold Brown-out reset threshold Brown-out reset hysteresis
VIT+ VITVHYS(BOR)
1. Guaranteed by design, not tested in production 2. TBD = To be determined 3. Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the minimum operating voltage (VDD min) when the tTEMP delay has elapsed.
11.3.1
Supply current characteristics
The current consumption is measured as described in Figure 8 on page 54 and Figure 9 on page 55.
Total current consumption
The MCU is placed under the following conditions:

All I/O pins in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except if explicitly mentioned.
Subject to general operating conditions for VDD and TA.
Note on the run-current typical and worst-case values
Typical device currents values are representative of an application set-up without any I/O activity at 25 C. The worst case values correspond to the actual test-limits and include both internal and external device I/O current. During the execution of an actual application program, the number of read access cycles to the code memory depends on its structure. A code doing arithmetical calculations reads the memory less frequently than programs with jump, loop or data manipulation instructions. The fast-reading access in a Flash memory needs much more power compared to a RAM. Consequently, the run-current for EEPROM execution depends strongly on the actual application code structure. The measurements in the tables below were made using a short, representative code with move, jump and arithmetic operations. The worst case, an infinite loop of `while' instructions takes approximately 25 % more power. For RAM execution, such power to program structure relations has not been observed.
58/100
STM8AF61xx, STM8AF51xx Table 19.
Symbol
Electrical characteristics
Total current consumption in run, wait and slow mode at VDD = 5.0 V
Parameter Conditions HSE Crystal oscillator fCPU = fMASTER = 24 MHz HSE external clock fCPU = fMASTER = 24 MHz Supply current in run mode HSE Crystal oscillator All peripherals off, fCPU = fMASTER = 16 MHz code executed HSE external clock from RAM fCPU = fMASTER = 16 MHz HSI internal RC fCPU = fMASTER = 16 MHz HSI internal RC 16 MHz/8 fCPU = fMASTER = 2 MHz HSE Crystal oscillator fCPU = fMASTER = 24 MHz HSE external clock fCPU = fMASTER = 24 MHz Supply current in run mode HSE Crystal oscillator All peripherals off, fCPU = fMASTER = 16 MHz code executed HSE external clock from EEPROM fCPU = fMASTER = 16 MHz HSI internal RC fCPU = fMASTER = 16 MHz HSI internal RC 16 MHz/8 fCPU = fMASTER = 2 MHz HSE Crystal oscillator fCPU = fMASTER = 24 MHz HSE external clock fCPU = fMASTER = 24 MHz Supply current in run mode HSE Crystal oscillator All peripherals on, fCPU = fMASTER = 16 MHz code executed HSE external clock from RAM fCPU = fMASTER = 16 MHz HSI internal RC fCPU = fMASTER = 16 MHz HSI internal RC 16 MHz/8 fCPU = fMASTER = 2 MHz Typ 4.4 3.8 3.3 mA 2.7 2.55 1.2 11.4 10.8 9.0 mA 8.35 8.2 1.9 6.9 6.3 4.3 mA 3.7 3.5 1.2 8.0(1) 15.0(1) 6.0(1) Max Unit
IDD(RUN)
IDD(RUN)
IDD(RUN)
59/100
Electrical characteristics Table 19.
Symbol
STM8AF61xx, STM8AF51xx
Total current consumption in run, wait and slow mode at VDD = 5.0 V
Parameter Conditions HSE Crystal oscillator fCPU = fMASTER = 24 MHz HSE external clock fCPU = fMASTER = 24 MHz Supply current in run mode HSE Crystal oscillator All peripherals on, fCPU = fMASTER = 16 MHz code executed HSE external clock from EEPROM fCPU = fMASTER = 16 MHz HSI internal RC fCPU = fMASTER = 16 MHz HSI internal RC 16 MHz/8 fCPU = fMASTER = 2 MHz HSE Crystal oscillator fCPU = fMASTER = 24 MHz HSE external clock fCPU = fMASTER = 24 MHz Supply current in wait mode HSE Crystal oscillator fCPU = fMASTER = 16 MHz HSE external clock fCPU = fMASTER = 16 MHz HSI internal RC fCPU = fMASTER = 16 MHz HSI internal RC 16 MHz/8 fCPU = fMASTER = 2 MHz HSE external clock 16 MHz/128 fCPU = fMASTER = 0.125 MHz Typ 13.9 13.3 10.0 mA 9.35 9.2 2.1 2.4 1.8 2.0 mA 1.38 1.21 1.05 1.15 1.04 0.5 mA 1.21 1.09 0.56 4.0(1) 4.0(1) Max Unit
IDD(RUN)
IDD(WFI)
CPU not clocked, all peripherals off
Supply IDD(SLOW) current in slow mode
fCPU scaled down, all peripherals off, HSI internal RC 16 MHz/128 fCPU = fMASTER = 0.125 MHz code executed from RAM LSI internal RC 128 kHz fCPU = fMASTER = 0.128 MHz
fCPU scaled down, all peripherals off, HSI internal RC 16 MHz/128 fCPU = fMASTER = 0.125 MHz code executed from EEPROM LSI internal RC 128 kHz fCPU = fMASTER = 0.128 MHz
1. Prodution test limits
HSE external clock 16 MHz/128 fCPU = fMASTER = 0.125 MHz
60/100
STM8AF61xx, STM8AF51xx Table 20.
Symbol IDD(H)
Electrical characteristics
Total current consumption and timing in halt, fast active halt and slow active halt modes at VDD = 5.0 V
Parameter Supply current in halt mode Flash in stand-by mode Crystal osc 16 MHz/128 Supply current in fast active halt mode Supply current in slow active halt mode Wake-up time from fast active halt mode to run mode Wake-up time from slow active halt mode to run mode 64 1050 490 150 11 200(1) 30(1) 2(2) s 100
(2)
Conditions Flash powered down
Typ 6.5
Max 10(1)
Unit
IDD(FAH)
HSE osc 16 MHz/128 LSI RC 128 kHz
A
IDD(SAH) tWU(FAH) tWU(SAH)
LSI RC 128 kHz
1. Maximum values at 55 C, tested in production according to the actual product temperature ranges. 2. Data based on characterization results, not tested in production.
Table 21.
Symbol
Total current consumption in run, wait and slow mode at VDD = 3.3 V
Parameter Conditions HSE Crystal oscillator fCPU = fMASTER = 24 MHz HSE external clock fCPU = fMASTER = 24 MHz Supply current in run mode HSE Crystal oscillator All peripherals off, fCPU = fMASTER = 16 MHz code executed HSE external clock from RAM fCPU = fMASTER = 16 MHz HSI internal RC fCPU = fMASTER = 16 MHz HSI internal RC 16 MHz/8 fCPU = fMASTER = 2 MHz Typ 4 3.8 2.9 mA 2.7 2.55 1.2 Max Unit
IDD(RUN)
61/100
Electrical characteristics Table 21.
Symbol
STM8AF61xx, STM8AF51xx
Total current consumption in run, wait and slow mode at VDD = 3.3 V
Parameter Conditions HSE Crystal oscillator fCPU = fMASTER = 24 MHz HSE external clock fCPU = fMASTER = 24 MHz Supply current in run mode HSE Crystal oscillator All peripherals off, fCPU = fMASTER = 16 MHz code executed HSE external clock from EEPROM fCPU = fMASTER = 16 MHz HSI internal RC fCPU = fMASTER = 16 MHz HSI internal RC 16 MHz/8 fCPU = fMASTER = 2 MHz HSE Crystal oscillator fCPU = fMASTER = 24 MHz HSE external clock fCPU = fMASTER = 24 MHz Supply current in run mode HSE Crystal oscillator All peripherals on, fCPU = fMASTER = 16 MHz code executed HSE external clock from RAM fCPU = fMASTER = 16 MHz HSI internal RC fCPU = fMASTER = 16 MHz HSI internal RC 16 MHz/8 fCPU = fMASTER = 2 MHz HSE Crystal oscillator fCPU = fMASTER = 24 MHz HSE external clock fCPU = fMASTER = 24 MHz Supply current in run mode HSE Crystal oscillator All peripherals on, fCPU = fMASTER = 16 MHz code executed HSE external clock from EEPROM fCPU = fMASTER = 16 MHz HSI internal RC fCPU = fMASTER = 16 MHz HSI internal RC 16 MHz/8 fCPU = fMASTER = 2 MHz Typ 11.0 10.8 8.6 mA 8.35 8.2 1.6 6.5 6.3 3.9 mA 3.7 3.55 1.4 13.5 13.3 9.6 mA 9.35 9.2 1.8 Max Unit
IDD(RUN)
IDD(RUN)
IDD(RUN)
62/100
STM8AF61xx, STM8AF51xx Table 21.
Symbol
Electrical characteristics
Total current consumption in run, wait and slow mode at VDD = 3.3 V
Parameter Conditions HSE Crystal oscillator fCPU = fMASTER = 24 MHz HSE external clock fCPU = fMASTER = 24 MHz Supply current in wait mode HSE Crystal oscillator fCPU = fMASTER = 16 MHz HSE external clock fCPU = fMASTER = 16 MHz HSI internal RC fCPU = fMASTER = 16 MHz HSI internal RC 16 MHz/8 fCPU = fMASTER = 2 MHz HSE external clock 16 MHz/128 fCPU = fMASTER = 0.125 MHz Typ 2.0 1.8 1.6 mA 1.38 1.21 1.05 1.15 1.04 0.5 mA 1.21 1.09 0.56 Max Unit
IDD(WFI)
CPU not clocked, all peripherals off
Supply IDD(SLOW) current in slow mode
fCPU scaled down, all peripherals off, HSI internal RC 16 MHz/128 fCPU = fMASTER = 0.125 MHz code executed from RAM LSI internal RC 128 kHz fCPU = fMASTER = 0.128MHz
fCPU scaled down, all peripherals off, HSI internal RC 16 MHz/128 fCPU = fMASTER = 0.125 MHz code executed from EEPROM LSI internal RC 128 kHz fCPU = fMASTER = 0.128 MHz
HSE external clock 16 MHz/128 fCPU = fMASTER = 0.125 MHz
63/100
Electrical characteristics Table 22.
Symbol IDD(H)
STM8AF61xx, STM8AF51xx
Total current consumption and timing in halt, fast active halt and slow active halt modes at VDD = 3.3 V
Parameter Supply current in halt mode Flash in stand-by mode Crystal osc 16 MHz/128 Supply current in fast active halt mode Supply current in slow active halt mode Wake-up time from fast active halt mode to run mode Wake-up time from slow active halt mode to run mode 62 600 490 140 9 2(1) s 100
(1)
Conditions Flash powered down
Typ 4.7
Max
Unit
IDD(FAH)
HSE osc 16 MHz/128 LSI RC 128 kHz
A
IDD(SAH) tWU(FAH) tWU(SAH)
LSI RC 128 kHz
1. Data based on characterization results, not tested in production
64/100
STM8AF61xx, STM8AF51xx
Electrical characteristics
On-chip peripherals
Table 23.
Symbol
Typical peripheral current consumption VDD = 5.0 V(1)
Typ. Parameter Typ. Typ.
fmaster =
2 MHz 0.03 0.02 0.01 0.004 0.03 0.03 0.01 0.02 0.06 0.003 0.22 0.93 2.5
fmaster =
16 MHz 0.23 0.12 0.1 0.03 0.09 0.11 0.04 0.06 0.22 0.02 1 0.95 2.9
fmaster =
24 MHz 0.34 0.19 0.16 0.05 0.15 0.18 0.07
Unit
IDD(TIM1) IDD(TIM2) IDD(TIM3) IDD(TIM4) IDD(USART) IDD(LINUART) IDD(SPI) IDD(I2C) IDD(CAN) IDD(AWU) IDD(TOT_DIG) IDD(ADC) IDD(EE_PROG)
TIM1 supply current(2) TIM2 supply current (2) TIM3 supply current(2) TIM4 supply current(2) USART supply current(2) LINUART supply current(2) SPI supply current(2) I2C supply current(2) CAN supply current(3) AWU supply current(2) All digital peripherals on ADC supply current when converting(4) Data EEPROM programming current
mA 0.91 0.34 0.05 2.4 0.96 3.1
1. Typical values - not tested in production. Since the peripherals are powered by an internally regulated, constant digital supply voltage, the values are similar in the full supply voltage range. 2. Data based on a differential IDD measurement between no peripheral clocked and a single active peripheral. This measurement does not include the pad toggling consumption. 3. Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data transmit sequence in loopback mode at 1 MHz. This measurement does not include the pad toggling consumption. 4. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
65/100
Electrical characteristics
STM8AF61xx, STM8AF51xx
Current consumption curves
Figure 11 to Figure 16 show typical current consumption measured with code executing in RAM. Figure 11. Typ. IDD(RUN)HSE vs. VDD @fCPU = 16 MHz, periph = on
10 9
Figure 12. Typ. IDD(RUN)HSE vs. fCPU @ VDD = 5.0 V, periph = on
10 9
25C 85C 125C
25C 85C 125C
IDD(RUN)HSE [mA]
8 7 6 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5
IDD(RUN)HSE [mA]
8 7 6 5 4 3 2 1 0
5.5
6
0
5
10
15
20
25
30
VDD [V]
fcpu [MHz]
Figure 13. Typ. IDD(RUN)HSI vs. VDD @ fCPU = 16 MHz, periph = off
IDD(RUN)HSI [mA] 4 3 2 1 0 2.5 3.5 4.5 VDD [V] 5.5 25C 85C 125C 6.5
Figure 14. Typ. IDD(WFI)HSE vs. VDD @ fCPU = 16 MHz, periph = on
IDD(WFI)HSE [mA] 6 5 4 3 2 1 0 2.5 3.5 4.5 VDD [V] 5.5 25C 85C 125C 6.5
Figure 15. Typ. IDD(WFI)HSE vs. fCPU @ VDD = 5.0 V, periph = on
6
Figure 16. Typ. IDD(WFI)HSI vs. VDD @ fCPU = 16 MHz, periph = off
2.5
IDD(WFI)HSE [mA]
5 4 3 2 1 0 0 5 10 15 20 25 30
IDD(WFI)HSI [mA]
2
1.5
1
25C 85C 125C
25C
0.5
85C 125C
0 2.5 3 3.5 4 4.5 5 5.5 6
fcpu [MHz]
VDD [V]
66/100
STM8AF61xx, STM8AF51xx
Electrical characteristics
11.3.2
External clock sources and timing characteristics
HSE user external clock
Subject to general operating conditions for VDD and TA. Table 24.
Symbol fHSE_ext VHSEdHL VHSEH VHSEL ILEAK_HSE
HSE user external clock characteristics
Parameter User external clock source frequency Comparator hysteresis OSCIN input pin high level voltage OSCIN input pin low level voltage OSCIN input leakage current VSS < VIN < VDD Conditions TA < 105 C TA > 105 C Min 0(1) 0
(1)
Typ
Max 24
Unit MHz
16 V VDD V 0.3 x VDD +1 A
0.1 x VDD 0.7 x VDD VSS -1
1. In case of CSS, the external clock must have a frequency above 500 kHz.
Figure 17. HSE external clock source
VHSEH VHSEL
fHSE External clock source OSCIN STM8A
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied using a crystal/ceramic resonator oscillator of up to 24 MHz. All the information given in this paragraph is based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal resonator manufacturer for more details (frequency, package, accuracy...).
67/100
Electrical characteristics Table 25.
Symbol RF C(1)
STM8AF61xx, STM8AF51xx
HSE oscillator characteristics
Parameter Feedback resistor Recommended load capacitance(2) C = 20 pF Conditions Min Typ 220 20 6 (startup) 2 (stabilized) mA C = 10 pF 6 (startup) 1.5 (stabilized) 5 VDD is stabilized 1 mA/V ms Max Unit k pF
IDD(HSE)
HSE oscillator power consumption
gm
Oscillator transconductance
tSU(HSE)(3) Startup time
1. C is approximately equivalent to 2 x crystal Cload.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value. Refer to crystal manufacturer for more details 3. tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 24 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Figure 18. HSE oscillator circuit diagram
Rm Lm Cm Resonator Consumption control CO CL1 OSCIN gm RF fHSE to core
Resonator
OSCOUT CL2
STM8A
HSE oscillator critical gm formula
g mcrit = ( 2 x x HSE ) x R m ( 2Co + C )
f 2 2
Rm: Notional resistance (see crystal specification) Lm: Notional inductance (see crystal specification) Cm: Notional capacitance (see crystal specification) Co: Shunt capacitance (see crystal specification) CL1 = CL2 = C: Grounded external capacitance gm >> gmcrit
68/100
STM8AF61xx, STM8AF51xx
Electrical characteristics
11.3.3
Internal clock sources and timing characteristics
Subject to general operating conditions for VDD and TA.
High speed internal RC oscillator (HSI)
Table 26.
Symbol fHSI
HSI oscillator characteristics
Parameter Frequency HSI oscillator user trimming accuracy Trimmed by the application for any VDD and TA conditions VDD = 5.0 V, TA = 25C VDD = 5.0 V, 25 C TA 85 C VDD = 5.0 V, 25 C TA 125 C VDD = 3.0 V VDD 5.5 V, -40 C TA 125 C -3(1) -5(1) -1(1) -1(1) 2 3(1) 5(1) 2(2) s Conditions Min Typ 16 1(1) 1(1) % Max Unit MHz
ACCHS HSI oscillator accuracy (factory calibrated)
tsu(HSI)
HSI oscillator wake-up time including calibration
1. Tested in production 2. Guaranteed by design, not tested in production
Figure 19. Typical HSI frequency vs VDD @ four temperatures
3%
-40C
HSI frequency variation [%] 2% 1% 0% -1% -2% -3% 2.5 3 3.5 4 VDD [V] 4.5 5 5.5 6
25C 85C 125C
69/100
Electrical characteristics
STM8AF61xx, STM8AF51xx
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for VDD and TA.
Table 27.
Symbol fLSI tsu(LSI) Frequency LSI oscillator wake-up time
LSI oscillator characteristics
Parameter Conditions Min 112 Typ 128 Max 144 7(1) Unit kHz s
1. Data based on characterization results, not tested in production.
Figure 20. Typical LSI frequency vs VDD @ room temperature
3% 2% 1% 0% -1% -2% -3% 2.5 3 3.5 4 VDD [V] 4.5 5 5.5 6
LSI frequency variation [%]
25C
70/100
STM8AF61xx, STM8AF51xx
Electrical characteristics
11.3.4
Memory characteristics
RAM and hardware registers
Table 28.
Symbol VRM
RAM and hardware registers
Parameter Data retention mode(1) Conditions Halt mode (or reset) Min 1.8 Typ Max Unit V
1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production. refer to Table 18 on page 58 for the value of VIT-max
Flash program memory/data EEPROM memory
General conditions: TA = -40 to 125 C.
Table 29.
Symbol VDD
Flash program memory/data EEPROM memory
Parameter Conditions fCPU 24 MHz Min(1) Typ 3.0 Max 5.5 Unit V
Operating voltage (all modes, execution/write/erase) Standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) Fast programming time for 1 block (128 bytes)
6
6.6
ms
tprog
3 3 TA = 25 C TA = 125 C TA = 25 C TA = 125 C TA = 145 C TA = 25 C TA = 55 C TA = 85 C 1k 100 300 k 100 k 80 k 40 20 10 1000 40 20 10
3.3 3.3
ms ms
terase
Erase time for 1 block (128 bytes) Program memory endurance erase/write cycles(2)
NRW Data memory endurance erase/write cycles(2)
cycles
Program memory after cycling tRET Data memory retention after cycling at the endurance limits (T, n)
years
Full temperature range TA = 25 C
hours
tRETI
Intrinsic data retention
TA = 55 C TA = 85 C
years
1. Guaranteed by characterization, not tested in production. 2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte.
71/100
Electrical characteristics
STM8AF61xx, STM8AF51xx
11.3.5
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or an external pull-up or pull-down resistor.
Table 30.
Symbol VIL VIH Vhys VOH
I/O static characteristics
Parameter Input low level voltage Input high level voltage Hysteresis(1) I = 3 mA I = 1.5 mA I = 8mA Standard I/0, VDD = 5 V Standard I/0, VDD = 3 V High sink and true open drain I/0, VDD = 5 V Standard I/0, VDD = 5 V Standard I/0, VDD = 3 V VDD = 5 V, VIN = VSS Fast I/Os Load = 50 pF Standard and high sink I/Os Load = 50 pF VSS VIN VDD VSS VIN VDD -40 C < TA < 125 C Injection current 4 mA 35 50 VDD - 0.5 V VDD - 0.4 V 0.5 0.6 0.4 65 20(2) 125(2) k ns ns V VDD = 5.0 V Conditions Min -0.3 V 0.7 x VDD 0.1 x VDD Typ Max 0.3 x VDD VDD + 0.3 V Unit V V mV
VOL
I = 3 mA I = 1.5 mA
Rpu
Pull-up resistor
tR, tF
Rise and fall time (10% - 90%)
Ilkg
Input leakage current, analog and digital Analog input leakage current Leakage current in adjacent I/O(2)
1(2)
A
Ilkg ana Ilkg(inj)
250(2) 1(2)
nA A
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. 2. Data based on characterization results, not tested in production.
72/100
STM8AF61xx, STM8AF51xx Figure 21. Typical VIL and VIH vs VDD @ four temperatures
6
Electrical characteristics
-40C
5 4 VIL / V IH [V] 3 2 1 0 2.5 3 3.5 4 VDD [V] 4.5 5 5.5 6
25C 85C 125C
Figure 22. Typical pull-up resistance RPU vs VDD @ four temperatures
60 55 Pull-Up resistance [k ohm] 50 45 40 35 30 2.5 3 3.5 4 VDD [V] 4.5 5 5.5 6
-40C 25C 85C 125C
Figure 23. Typical pull-up current Ipu vs VDD @ four temperatures
140 120 Pull-Up current [A] 100 80 60 40 20 0 0 1 2 3 VDD [V]
Note: The pull-up is a pure resistor (slope goes through 0).
-40C 25C 85C 125C
4
5
6
73/100
Electrical characteristics
STM8AF61xx, STM8AF51xx
Typical output level curves
Figure 24 to Figure 33 show typical output level curves measured with output on a single pin. Figure 24. Typ. VOL @ VDD = 3.3 V (standard ports)
1.5 1.25 1 VOL [V] 0.75 0.5 0.25 0 0 1 2 3 IOL [mA] 4 5 6 7 VOL [V]
Figure 25. Typ. VOL @ VDD = 5.0 V (standard ports)
1.5 1.25 1 0.75 0.5 0.25 0 0 2 4 6 IOL [mA] 8 10 12
-40C 25C 85C 125C
-40C 25C 85C 125C
Figure 26. Typ. VOL @ VDD = 3.3 V (true open drain ports)
2 1.75 1.5 1.25 VOL [V] 1 0.75 0.5 0.25 0 0 2 4 6 IOL [mA] 8 10 12 14
Figure 27. Typ. VOL @ VDD = 5.0 V (true open drain ports)
2 1.75 1.5 1.25 VOL [V] 1 0.75 0.5 0.25 0 0 5 10 IOL [mA] 15 20 25
-40C 25C 85C 125C
-40C 25C 85C 125C
Figure 28. Typ. VOL @ VDD = 3.3 V (high sink ports)
1.5 1.25 1 VOL [V] 0.75 0.5 0.25 0 0 2 4 6 IOL [mA] 8 10 12 14
Figure 29. Typ. VOL @ VDD = 5.0 V (high sink ports)
1.5 1.25 1 VOL [V] 0.75 0.5 0.25 0 0 5 10 IOL [mA] 15 20 25
-40C 25C 85C 125C
-40C 25C 85C 125C
74/100
STM8AF61xx, STM8AF51xx
Electrical characteristics
Figure 30. Typ. VDD - VOH @ VDD = 3.3 V (standard ports)
2 1.75 1.5 VDD - V OH [V] 1.25 1 0.75 0.5 0.25 0 0 1 2 3 IOH [mA] 4 5 6 7
Figure 31. Typ. VDD - VOH @ VDD = 5.0 V (standard ports)
2 1.75 1.5 VDD - V OH [V] 1.25 1 0.75 0.5 0.25 0 0 2 4 6 IOH [mA] 8 10 12
-40C 25C 85C 125C
-40C 25C 85C 125C
Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports)
2 1.75 1.5 VDD - V OH [V] 1.25 1 0.75 0.5 0.25 0 0 2 4 6 IOH [mA] 8 10 12 14
Figure 33. Typ. VDD - VOH @ VDD = 5.0 V (high sink ports)
2 1.75 1.5 VDD - V OH [V] 1.25 1 0.75 0.5 0.25 0 0 5 10 IOH [mA] 15 20 25
-40C 25C 85C 125C
-40C 25C 85C 125C
75/100
Electrical characteristics
STM8AF61xx, STM8AF51xx
11.3.6
Reset pin characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 31.
Symbol VIL(NRST) VIH(NRST) VOL(NRST) RPU(NRST) VF(NRST) VNF(NRST)
NRST pin characteristics
Parameter NRST input low level voltage(1) NRST input high level voltage(1) NRST output low level voltage(1) NRST pull-up resistor(3) NRST input filtered pulse(4) NRST input not filtered pulse(4) IOL=TBD(2) mA 30 40 TBD(2) TBD(2) Conditions Min VSS TBD(2) Typ Max TBD(2) VDD TBD(2) 60 k ns s V Unit
1. Data based on characterization results, not tested in production. 2. TBD = To be determined. 3. The RPU pull-up equivalent resistor is based on a resistive transistor 4. Data guaranteed by design, not tested in production.
Figure 34. Typical NRST VIL and VIH vs VDD @ four temperatures
-40C
6 5 4 VIL / V IH [V] 3 2 1 0 2.5 3 3.5 4 VDD [V] 4.5 5 5.5 6
25C 85C 125C
76/100
STM8AF61xx, STM8AF51xx
Electrical characteristics
Figure 35. Typical NRST pull-up resistance RPU vs VDD @ four temperatures
60 NRST Pull-Up resistance [k ohm] 55
-40C 25C 85C 125C
50 45 40
35 30 2.5 3 3.5 4 VDD [V] 4.5 5 5.5 6
Figure 36. Typical NRST pull-up current Ipu vs VDD @ four temperatures
140 120 NRST Pull-Up current [A] 100 80 60 40 20 0 0 1 2 3 VDD [V] 4 5 6
-40C 25C 85C 125C
The reset network shown in Figure 37 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 30. Otherwise the reset is not taken into account internally.
Figure 37. Recommended reset pin protection
VDD STM8A
RPU
External reset circuit 0.01 NRST
Filter
Internal reset
77/100
Electrical characteristics
STM8AF61xx, STM8AF51xx
11.3.7
TIM 1, 2, 3, and 4 timer characteristics
Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified.
Table 32.
Symbol tw(ICAP)in tres(TIM) fEXT ResTIM tCOUNTER tMAX_COUNT
TIM 1, 2, 3 characteristics
Parameter Input capture pulse time(1) Timer resolution time
(1) (1)
Conditions
Min 2 1
Typ
Max
Unit TMASTER TMASTER
Timer external clock frequency Timer resolution
(1)
24 16 1
MHz bit TMASTER
16-bit counter clock period when internal clock is selected(1) Maximum possible count(1)
65 536 TMASTER
1. Not tested in production
78/100
STM8AF61xx, STM8AF51xx
Electrical characteristics
11.3.8
SPI serial peripheral interface
Unless otherwise specified, the parameters given in Table 33 are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 33.
Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(NSS)(1) th(NSS)
(1)
SPI characteristics
Parameter SPI clock frequency Slave mode SPI clock rise and fall time Capacitive load: C = 30 pF NSS setup time NSS hold time SCK high and low time Slave mode Slave mode Master mode, fMASTER = 16 MHz, fSCK= 8 MHz Master mode Data input setup time Slave mode Master mode, fMASTER = 16 MHz, fSCK = 8 MHz Slave mode, fMASTER = 16 MHz, fSCK = 8 MHz Data output access time Slave mode, fMASTER = 16 MHz, fSCK = 8 MHz Slave mode 2 7 3 400 4*tMASTER 25 100 3 100 6 ns 4*TMASTER 70 110 5 140 0 10 25 Conditions Master mode Min 0 Max 10 MHz Unit
tw(SCKH)(1) tw(SCKL)(1) tsu(MI)(1) tsu(SI)(1) th(MI)(1) th(SI)(1)
Data input hold time
ta(SO)(1)(2) tdis(SO)(1)(3) tv(SO)(1) tv(MO)(1) th(SO)(1) th(MO)(1)
Data output disable time Data output valid time Data output valid time
Slave mode Slave mode (after enable edge), fMASTER = 16 MHz, fSCK = 8 MHz Master mode (after enable edge), fMASTER = 16 MHz, fSCK = 8 MHz Slave mode (after enable edge)
Data output hold time Master mode (after enable edge)
1. Values based on design simulation and/or characterization results, and not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
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Electrical characteristics Figure 38. SPI timing diagram - slave mode and CPHA = 0
STM8AF61xx, STM8AF51xx
NSS input tSU(NSS) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tc(SCK) th(NSS)
tw(SCKH) tw(SCKL) tv(SO) MS B O UT tsu(SI) tr(SCK) tf(SCK) LSB OUT
ta(SO) MISO OUT P UT MOSI I NPUT
th(SO) BI T6 OUT
tdis(SO)
M SB IN th(SI)
B I T1 IN
LSB IN
ai14134
Figure 39. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input tSU(NSS) SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) th(NSS)
tw(SCKH) tw(SCKL) tr(SCK) tf(SCK)
ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN
tv(SO) MS B O UT th(SI)
th(SO) BI T6 OUT
tdis(SO) LSB OUT
B I T1 IN
LSB IN
ai14135
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
80/100
STM8AF61xx, STM8AF51xx Figure 40. SPI timing diagram - master mode(1)
High NSS input tc(SCK) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1
Electrical characteristics
SCK Input
CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT MOSI OUTUT tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO)
ai14136
tr(SCK) tf(SCK) BI T6 IN LSB IN
LSB OUT
1. Measurement points are at CMOS levels: 0.3 VDD and 0.7 VDD.
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Electrical characteristics
STM8AF61xx, STM8AF51xx
11.3.9
I2C interface characteristics
Table 34.
Symbol
I2C characteristics
Standard mode I2C Fast mode I2C(1) Parameter Min(2) Max(2) Min(2) 1.3 s SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time (VDD 3 ... 5.5 V) SDA and SCL fall time (VDD 3 ... 5.5 V) START condition hold time Repeated START condition setup time STOP condition setup time STOP to START condition time (bus free) Capacitive load for each bus line
I 2C
Unit Max(2)
tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb
SCL clock low time
4.7 4.0 250 0(3) 1000
0.6 100 0(4) 900(3) 300 ns
300 4.0 4.7 4.0 4.7 400
speed (400 kHz)
300 0.6 s 0.6 0.6 1.3 400 s s pF
1. fMASTER, must be at least 8 MHz to achieve max fast
2. Data based on standard I2C protocol requirement, not tested in production 3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL
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STM8AF61xx, STM8AF51xx
Electrical characteristics
11.3.10
10-bit ADC characteristics
Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified.
Table 35.
Symbol fADC VDDA VREF+ VREF-
ADC characteristics
Parameter ADC clock frequency Analog supply Positive reference voltage Negative reference voltage 3 2.75 VSSA VSSA Conditions Min Typ 2 5.5 VDDA 0.5 VDDA VREF+ Max Unit MHz V V V V V
VAIN
Conversion voltage range(1)
Devices with external VREF+/ VREF- pins
VREF-
CADC tS(1) tSTAB tCONV
Internal sample and hold capacitor Sampling time (3 x 1/fADC) Wake-up time from standby Total conversion time including sampling time (14 x 1/fADC) fADC = 2 MHz fADC = 2 MHz
3 1.5 7 7
pF s s s
1. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming.
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Electrical characteristics Table 36.
Symbol |ET| |EO| |EG| |ED| |EL|
STM8AF61xx, STM8AF51xx
ADC accuracy with RAIN < 10 k RAIN, VDDA = 3.3 V
Parameter Total unadjusted error(1) Offset error(1) Gain error(1) Differential linearity error(1) Integral linearity error(1) fADC = 2 MHz Conditions Typ 1.5 1.1 -0.2/0.6 0.9 1 Max TBD(1) TBD(1) TBD(1) TBD(1) TBD(1) LSB Unit
1. TBD = To be determined
Table 37.
Symbol |ET| |EO| |EG| |ED| |EL|
ADC accuracy with RAIN < 10 k , VDDA = 5 V
Parameter Total unadjusted error(1) Offset error(1) Gain error(1) Differential linearity error(1) Integral linearity error(1) fADC = 2 MHz Conditions Typ 1.4 0.8 0.1 0.9 0.7 Max 3 2 1 2 2 LSB Unit
1. ADC accuracy vs. injection current: Any positive or negative injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 11.3.5 does not affect the ADC accuracy.
Figure 41. ADC accuracy characteristics
1023 1022 1021 1LSB IDEAL
-V V DDA SSA = ---------------------------------------1024
EG
(2) 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL 5 6 7 1021102210231024 EO EL ED ET (3) (1)
VDDA
1. Example of an actual transfer curve 2. The ideal transfer curve 3. End point correlation line ET = Total unadjusted error: Maximum deviation between the actual and the ideal transfer curves. EO = Offset error: Deviation between the first actual transition and the first ideal one. EG = Gain error: Deviation between the last ideal transition and the last actual one. ED = Differential linearity error: Maximum deviation between actual steps and the ideal one. EL = Integral linearity error: Maximum deviation between any actual transition and the end point correlation line.
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STM8AF61xx, STM8AF51xx Figure 42. Typical application with ADC
VDD VT 0.6V AINx CAIN VT 0.6V
Electrical characteristics
STM8A
RAIN VAIN
10-bit A/D conversion IL 1 CADC
11.3.11
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard. FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:

Corrupted program counter Unexpected reset Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
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Electrical characteristics Table 38.
Symbol
STM8AF61xx, STM8AF51xx
EMS data
Parameter Conditions Level/class
VFESD
VDD = 3.3 V, TA= 25 C, Voltage limits to be applied on any I/O pin to fMASTER = 16 MHz (HSI clock), induce a functional disturbance Conforms to IEC 1000-4-2 Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD= 3.3 V, TA= 25 C, fMASTER = 16 MHz (HSI clock), Conforms to IEC 1000-4-4
3B
VEFTB
4A
Electromagnetic interference (EMI)
Emission tests conform to the SAE J 1752/3 standard for test software, board layout and pin loading.
Table 39. EMI data
Conditions Symbol Parameter General conditions Max fCPU(1) 8 MHz 15 18 -1 2 16 MHz 17 22 3 2.5 24 MHz 22 16 5 2.5 dBV Unit
Monitored frequency band
SEMI
Peak level
SAE EMI level
VDD = 5 V, TA = 25 C, LQFP80 package conforming to SAE J 1752/3
0.1 MHz to 30 MHz 30 MHz to 130 MHz 130 MHz to 1 GHz
1. Data based on characterization results, not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181.
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STM8AF61xx, STM8AF51xx Table 40.
Symbol
Electrical characteristics
ESD absolute maximum ratings
Ratings Electrostatic discharge voltage (Human body model) Electrostatic discharge voltage (Charge device model) Electrostatic discharge voltage (Machine model) Conditions TA = 25C, conforming to JESD22-A114 TA= 25C, conforming to JESD22-C101 TA= 25C, conforming to JESD22-A115 Class Maximum Unit value(1) 4000 500 200 V
VESD(HBM) VESD(CDM) VESD(MM)
3A 3 B
1. Data based on characterization results, not tested in production
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up performance.

A supply overvoltage (applied to each power supply pin) and A current injection (applied to each input, output and configurable I/O pin) are performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.
Table 41.
Symbol
Electrical sensitivities
Parameter TA = 25 C Static latch-up class Conditions Class(1) A A A A
LU
TA = 85 C TA = 125 C TA = 145 C
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard).
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Electrical characteristics
STM8AF61xx, STM8AF51xx
11.4
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in Table 17: General operating conditions on page 57. The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x JA) Where: - - - - - TAmax is the maximum ambient temperature in C
JA is the package junction-to-ambient thermal resistance in C/W
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax) PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/Omax represents the maximum power dissipation on output pins Where: PI/Omax = (VOL*IOL) + ((VDD-VOH)*IOH), taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application.
Thermal characteristics(1)
Parameter Thermal resistance junction-ambient LQFP 80 - 14 x 14 mm Thermal resistance junction-ambient LQFP 64 - 10 x 10 mm Thermal resistance junction-ambient LQFP 48 - 7 x 7 mm Thermal resistance junction-ambient LQFP 32 - 7 x 7 mm Value 38 46 57 59 Unit C/W C/W C/W C/W
Table 42.
Symbol JA JA JA JA
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.
11.4.1
Reference document
JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org.
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STM8AF61xx, STM8AF51xx
Electrical characteristics
11.4.2
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see Figure 47: STM8A order codes on page 95). The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions: Maximum ambient temperature TAmax= 82 C (measured according to JESD51-2), IDDmax = 8 mA, VDD = 5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 8 mA x 5 V= 400 mW PIOmax = 20 x 8 mA x 0.4 V = 64 mW This gives: PINTmax = 400 mW and PIOmax 64 mW: PDmax = 400 mW + 64 mW Thus: PDmax = 464 mW Using the values obtained in Table 42: Thermal characteristics on page 88 TJmax is calculated as follows: - For LQFP64 46C/W TJmax = 82 C + (46 C/W x 464 mW) = 82C + 21C = 103 C This is within the range of the suffix B version parts (-40 < TJ < 105 C). Parts must be ordered at least with the temperature range suffix B.
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Package characteristics
STM8AF61xx, STM8AF51xx
12
Package characteristics
To meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK(R) specifications are available at www.st.com.
90/100
STM8AF61xx, STM8AF51xx
Package characteristics
12.1
Package mechanical data
Figure 43. 80-pin low profile quad flat package (14 x 14)
D D1 A1 b A A2
e E1 E
L1 L
c
Table 43.
Dim.
80-pin low profile quad flat package mechanical data
mm Min Typ Max 1.60 0.05 1.35 0.22 0.09 16.00 14.00 16.00 14.00 0.65 0 0.45 3.5 0.60 1.00 7 0.75 0 0.0177 1.40 0.32 0.15 1.45 0.38 0.20 0.0020 0.0531 0.0087 0.0035 0.6299 0.5512 0.6299 0.5512 0.0256 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0126 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0150 0.0079
A A1 A2 b c D D1 E E1 e L L1
1. Values in inches are converted from mm and rounded to 4 decimal digits
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Package characteristics Figure 44. 64-pin low profile quad flat package (10 x 10)
D D1
STM8AF61xx, STM8AF51xx
A A2 A1 Seating plane (0.1 x 0.004 mm)
b
e E1 E
c M x 45 Pin 1 identification L1 L
1. Available only for STM8A products with up to 64 Kbytes Flash
Table 44.
Dim.
64-pin low profile quad flat package mechanical data
mm Min Typ Max 1.60 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 0 0.45 3.5 0.60 1.00 7 0.75 0 0.0177 1.40 0.22 0.15 1.45 0.27 0.20 0.0020 0.0531 0.0067 0.0035 0.4724 0.3937 0.4724 0.3937 0.0197 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079
A A1 A2 b c D D1 E E1 e L L1
1. Values in inches are converted from mm and rounded to 4 decimal digits
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STM8AF61xx, STM8AF51xx Figure 45. 48-pin low profile quad flat package (7 x 7)
Package characteristics
A D D1 A1 b A2
e E1 E
L1 L
c
Table 45.
Dim.
48-pin low profile quad flat package mechanical data
mm Min Typ Max 1.60 0.05 1.35 0.17 0.09 9.00 7.00 9.00 7.00 0.50 0 0.45 3.5 0.60 1.00 7 0.75 0 0.0177 1.40 0.22 0.15 1.45 0.27 0.20 0.0020 0.0531 0.0067 0.0035 0.3543 0.2756 0.3543 0.2756 0.0197 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079
A A1 A2 b c D D1 E E1 e L L1
1. Values in inches are converted from mm and rounded to 4 decimal digits
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Package characteristics Figure 46. 32-pin low profile quad flat package (7 x 7)
D D1
STM8AF61xx, STM8AF51xx
A A2 A1
e
E1 E
b
L1 L
c
Table 46.
Dim.
32-pin low profile quad flat package mechanical data
mm Min Typ Max 1.60 0.05 1.35 0.30 0.09 9.00 7.00 9.00 7.00 0.80 0 0.45 3.5 0.60 1.00 7 0.75 0 0.0177 1.40 0.37 0.15 1.45 0.45 0.20 0.0020 0.0531 0.0118 0.0035 0.3543 0.2756 0.3543 0.2756 0.0315 3.5 0.0236 0.0394 7 0.0295 0.0551 0.0146 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0177 0.0079
A A1 A2 b c D D1 E E1 e L L1
1. Values in inches are converted from mm and rounded to 4 decimal digits
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STM8AF61xx, STM8AF51xx
Ordering information
13
Ordering information
Figure 47. STM8A order codes
STM8A F 51 A A T D xxx(1) Y
Product family STM8A....8-bit microcontroller Memory size Program memory type F....Flash + EEPROM P....FASTROM no EEPROM H....Flash no EEPROM Q....FASTROM + EEPROM
Device family 5x - CAN/LIN 6x - LIN only
Temperature range Pin count 3....20 pins 6....32 pins 7....44 pins 8....48 pins 9....64 pins A....80 pins B....100 pins C....128 pins A....-40 C to +85 C B....-40 C to +105 C C....-40 C to +125 C D....-40 C to +145 C
2....8 Kbyte 4....16 Kbyte 6....32 Kbyte 7....48 Kbyte 8....64 Kbyte 9....96 Kbyte A....128 Kbyte B....256 Kbyte
Package type T.....LQFP U....QFN
Packaging Y.... Tray U.... Tube R.... Tape and reel X.... Tape and reel x90
1. Customer specific FASTROM code
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STM8 development tools
STM8AF61xx, STM8AF51xx
14
STM8 development tools
Development tools for the STM8A microcontrollers include the STice emulation system offering tracing and code profiling

STVD high-level language debugger including assembler and visual development environment - seamless integration of third party C compilers
STVP Flash programming software In addition, the STM8A comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools.
14.1
Emulation and in-circuit debugging tools
The STM8 tool line includes the STice emulation system offering a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8A application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full-featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including tracing, profiling and code coverage analysis to help detect execution bottlenecks and dead code. In addition, STice offers in-circuit debugging and programming of STM8A microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller. For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers.
STice key features

Program and data trace recording up to 128 K records Advanced breakpoints with up to 4 levels of conditions Data breakpoints Real-time read/write of all device ressources during emulation Occurrence and time profiling and code coverage analysis (new features) In-circuit debugging/programming via SWIM protocol 8-bit probe analyzer 1 input and 2 output triggers USB 2.0 high speed interface to host PC Power supply follower managing application voltages between 1.62 to 5.5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Supported by free software tools that include integrated development environment (IDE), programming software interface and assembler for STM8
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STM8AF61xx, STM8AF51xx
STM8 development tools
14.2
Software tools
STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST visual develop (STVD) IDE and the ST visual programmer (STVP) software interface. STVD provides seamless integration of the Cosmic C compiler for STM8, which is available in a free version that outputs up to 16 Kbytes of code.
14.2.1
STM8 toolset
STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST visual develop - Full-featured integrated development environment from ST, featuring

Seamless integration of C and ASM toolsets Full-featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage
ST visual programmer (STVP) - Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8A microcontroller's Flash memory. STVP also offers project mode for saving programming configurations and automating programming sequences.
14.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. Available toolchains include:

C compiler for STM8 - Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.cosmic-software.com, www.raisonance.com STM8 assembler linker - Free assembly toolchain included in the STM8 toolset, which allows you to assemble and link your application source code.
14.3
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8A Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8A. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.
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Revision history
STM8AF61xx, STM8AF51xx
15
Revision history
Table 47.
Date 31-Jan-2008
Document revision history
Revision Rev 1 Initial release Added `H' products to the datasheet (Flash no EEPROM). Features on page 1: Updated Memories, Reset and supply management, Communication interfaces and I/Os; reduced wakeup pins by 1. Table 1: Removed STM8AF6168, STM8AF6148, STM8AF6166, STM8AF6146, STM8AF5168, STM8AF5186, STM8AF5176, and STM8AF5166. Section 1, Section 5, Section 6.2.1, Table 13, and Section 10: Updated reference documentation: RM0009, PM0047, and UM0470. Section 2: Added information about peak performance. Section 3: Removed STM8A common features table. Table 2: Removed STM8AF5186T, STM8AF5176T, STM8AF5168T, and STM8AF5166T. Table 3: Removed STM8AF6168T, STM8AF6166T, STM8AF6148T, and STM8AF6146T. Section 5: Made minor content changes and improved readability and layout. Section 5.4.3: Major modification, TMU included. Section 5.6.2: User triming updated. Section 5.6.3: LSI as CPU clock added. Section 5.6.4 , Section 5.6.5: Maximum frequency conditional 32 Kbyte/128 Kbyte. Section 5.8: Scan for 128 Kbyte removed. Section 5.9, Section 5.9.3: SPI 10 Mb/s. Figure 3, Figure 4, and Figure 5: Amended footnote 1. Table 5: HS output changed from 20 mA to 8 mA. Section 7: Corrected Figure 7: Register and memory map; removed address list; added Table 7. Section 11.3.1 Note on typical/WC values added. Table 10: Replaced the source blocks `simple USART', `very low-end timer (timer 4)', and `EEPROM' with `LINUART', `timer4' and `reserved' respectively, added TMU registers. Table 12: Updated OPT6 and NOPT6, added OPT7 to 17 (TMU, BL) Table 13: Updated OPT1 UBC[7:0], OPT4 CKAWUSEL, OPT4 PRSC [1:0], and OPT6, added OPT7 to 16 (TMU). Table 15: Amended footnotes. Table 17: Added parameter `voltage and current operating conditions'. Table 18: Amended footnotes. Table 19: Replaced. Table 20: Amended maximum data and footnotes. Table 21: Replaced. Table 22: Added and amended IDD(RUN) data; amended IDD(WFI) data; amended footnotes. Table 23: Filled in, amended maximum data and footnotes. Figure 11 to Figure 16: info on peripheral activity added. Table 24: Modified fHSE_ext data and added VHSEdhl data. Changes
22-Aug-2008
Rev 2
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STM8AF61xx, STM8AF51xx Table 47.
Date
Revision history
Document revision history (continued)
Revision Changes Table 26: Removed ACCHSI parameters and replaced with ACCHS parameters; amended data and footnotes. Table 28: Amended data. Table 29: Updated names and data of NRW and tRET parameters. Table 30: Added VOH and VOL parameters; Updated Ilkg ana parameter. Removed: Output driving current (standard ports), Output driving current (true open drain ports), and Output driving current (high sink ports). Table 35: Updated fADC, tS, and tCONV data. Table 36: Removed the 4-MHz condition from all parameters. Table 37: Removed the 4-MHz condition from all parameters; updated footnote 1 and removed footnote 2. Table 41: Added data for TA = 145 C. Figure 47: Updated memory size, pin count and package type information.
22-Aug-2008
Rev 2 cont'd
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STM8AF61xx, STM8AF51xx
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